Instruction Sets:

Characteristics and Functions

Addressing Modes
MIPS is a reduced instruction
set computer instruction set
architecture developed by MIPS
Computer Systems, now MIPS
Technologies, based in the
United States.
 What is an Instruction Set?
• The complete collection of instructions that
are understood by a CPU
• Machine language: binary representation of
operations and (addresses of) arguments
• Assembly language: mnemonic representation for
humans, e.g.,
OP A,B,C (meaning A <- OP(B,C))
 Elements of an Instruction
• Operation code (opcode)
– Do this: ADD, SUB, MPY, DIV, LOAD, STOR
• Source operand reference
– To this: (address of) argument of op, e.g.
register, memory location
• Result operand reference
– Put the result here (as above)
• Next instruction reference (often implicit)
– When you have done that, do this: BR
Overview
 Overview

load value

address
Types of instruction sets
Overview .. cont
Simple Instruction Format
(using two addresses)
Instruction Cycle State Diagram
 Design Decisions (1)
• Operation repertoire
– How many ops?
– What can they do?
– How complex are they?
• Data types (length of words, integer
representation)
• Instruction formats
– Length of op code field
– Length and number of addresses (e.g., implicit
addressing)
 Design Decisions (2)
• Registers
– Number of CPU registers available
– Which operations can be performed on which
registers? General purpose and specific
registers
• Addressing modes (see later)
• RISC v CISC
 Instruction Types
• Data transfer: registers, main memory,
stack or I/O
• Data processing: arithmetic, logical
• Control: systems control, transfer of
control
 Data Transfer
• Store, load, exchange, move, clear, set,
push, pop
• Specifies: source and destination (memory,
register, stack), amount of data
• May be different instructions for different
(size, location) movements, e.g.,
IBM S/390: L (32 bit word, R<-M), LH
(halfword, R<-M), LR (word, R<-R), plus
floating-point registers LER, LE, LDR, LD
Or one instruction and different
addresses, e.g. VAX: MOV
 Input/Output
• May be specific instructions, e.g. INPUT,
OUTPUT
• May be done using data movement
instructions (memory mapped I/O)
• May be done by a separate controller
(DMA): Start I/O, Test I/O
 Arithmetic
• Add, Subtract, Multiply, Divide for signed
integer (+ floating point and packed
decimal) – may involve data movement
• May include
– Absolute (|a|)
– Increment (a++)
– Decrement (a--)
– Negate (-a)
 Logical
• Bitwise operations: AND, OR, NOT, XOR,
TEST, CMP, SET
• Shifting and rotating functions, e.g.
– logical right shift for unpacking: send 8-bit
character from 16-bit word
– arithmetic right shift: division and truncation
for odd numbers
– arithmetic left shift: multiplication without
overflow
 Systems Control
• Privileged instructions: accessing control
registers or process table
• CPU needs to be in specific state
– Ring 0 on 80386+
– Kernel mode
• For operating systems use
 Transfer of Control
• Skip, e.g., increment and skip if zero:
ISZ Reg1, cf. jumping out from loop
• Branch instructions: BRZ X (branch to X if
result is zero), BRP X (positive), BRN X
(negative), BRE X,R1,R2 (equal)
• Procedure (economy and modularity): call
and return
Branch Instruction
Nested Procedure Calls
 Use of Stack:
Saving the return address for reentrant procedures
 Types of Operand
• Addresses: immediate, direct, indirect,
stack
• Numbers: integer or fixed point (binary,
twos complement), floating point (sign,
significand, exponent), (packed) decimal
(246 = 0000 0010 0100 0110)
• Characters: ASCII (128 printable and
control characters + bit for error detection)
• Logical Data: bits or flags, e.g., Boolean 0
and 1
 Pentium Data Types
• Addressing is by 8 bit unit
• General data types: 8 bit Byte, 16 bit word,
32 bit double word, 64 bit quad word
• Integer: signed binary using twos
complement representation
• (Un)packed decimal
• Near pointer: offset in segment
• Bit field
• Strings
• Floating point
 Instruction Formats
• Layout of bits in an instruction
• Includes opcode
• Includes (implicit or explicit) operand(s)
• Usually more than one instruction format
in an instruction set
 Instruction Length
• Affected by and affects:
– Memory size
– Memory organization - addressing
– Bus structure, e.g., width
– CPU complexity
– CPU speed
• Trade off between powerful instruction
repertoire and saving space
 Allocation of Bits
• Number of addressing modes: implicit or
additional bits specifying it
• Number of operands
• Register (faster, limited size and number,
32) versus memory
• Number of register sets, e.g., data and
address (shorter addresses)
• Address range
• Address granularity (e.g., by byte)
 Number of Addresses
• More addresses
– More complex (powerful?) instructions
– More registers - inter-register operations are
quicker
– Less instructions per program
• Fewer addresses
– Less complex (powerful?) instructions
– More instructions per program, e.g. data
movement
– Faster fetch/execution of instructions
• Example: Y=(A-B):[(C+(DxE)]
 3 addresses
Operation Result, Operand 1, Operand 2
– Not common
– Needs very long words to hold everything
SUB Y,A,B Y <- A-B
MPY T,D,E T <- DxE
ADD T,T,C T <- T+C
DIV Y,Y,T Y <- Y:T
 2 addresses
One address doubles as operand and result
– Reduces length of instruction
– Requires some extra work: temporary storage
MOVE Y,A Y <- A
SUB Y,B Y <- Y-B
MOVE T,D T <- D
MPY T,E T <- TxE
ADD T,C T <- T+C
DIV Y,T Y <- Y:T
 1 address
Implicit second address, usually a register
(accumulator, AC)
LOAD D AC <- D
MPY E AC <- ACxE
ADD C AC <-
AC+C
STOR Y Y <- AC
LOAD A AC <- A
SUB B AC <- AC-B
DIV Y AC <- AC:Y
 0 (zero) addresses

All addresses implicit, e.g. ADD

– Uses a stack, e.g. pop a, pop b, add
–c=a+b
 Addressing Modes
• Eight modes of addressing are available with the
C8051F020
• The different addressing modes determine how the
operand byte is selected
Addressing Modes Instruction
Register MOV A, B
Direct MOV 30H,A
Indirect ADD A,@R0
Immediate Constant ADD A,#80H
Relative* SJMP AHEAD
Absolute* AJMP BACK
Long* LJMP FAR_AHEAD
Indexed MOVC A,@A+PC

* Related to program branching instructions

 Addressing Modes

…How an
Instruction access /
get the operands to
be operated on
…Please remember this
Addressing modes
 Register Addressing
• The register addressing instruction
involves information transfer between
registers

• Example:
MOV R0, A

• The instruction transfers the accumulator

content into the R0 register. The register
bank (Bank 0, 1, 2 or 3) must be specified
prior to this instruction.
Register Addressing Diagram
Instruction
Opcode Register Address R
Registers

Operand
 Direct Addressing
• This mode allows you to specify the
operand by giving its actual memory
address (typically specified in hexadecimal
format) or by giving its abbreviated name
(e.g. P3)
Note: Abbreviated SFR names are defined in the “C8051F020.inc” header file

• Example:
MOV A, P3 ;Transfer the contents of
;Port 3 to the accumulator
MOV A, 020H ;Transfer the contents of
RAM ;location 20H to the
accumulator
 Direct Addressing Diagram
Instruction
Opcode Address A
Memory

Operand
 Indirect Addressing
• This mode uses a pointer to hold the effective address of the
operand
• Only registers R0, R1 and DPTR can be used as the pointer
registers
• The R0 and R1 registers can hold an 8-bit address, whereas
DPTR can hold a 16-bit address
• Examples:
MOV @R0,A ;Store the content of
;accumulator into the
memory ;location pointed
to by ;register R0. R0 could
have an ;8-bit address, such as
60H.
MOVX A,@DPTR ;Transfer the contents from
;the memory location
;pointed to by DPTR
into the ;accumulator. DPTR
could have a ;16-bit address, such as
1234H.
 Indirect Addressing Diagram
Instruction
Opcode Address A
Memory

Pointer to operand

Operand
 Immediate Constant Addressing
• This mode of addressing uses either an 8- or 16-bit
constant value as the source operand
• This constant is specified in the instruction, rather than in
a register or a memory location
• The destination register should hold the same data size
which is specified by the source operand
• Examples:
ADD A,#030H ;Add 8-bit value of 30H to
;the accumulator register
;(which is an 8-bit register).

MOV DPTR,#0FE00H ;Move 16-bit data constant

;FE00H into the 16-
bit Data ;Pointer
Register.
 Relative Addressing
• This mode of addressing is used with some type of jump
instructions, like SJMP (short jump) and conditional
jumps like JNZ
• These instructions transfer control from one part of a
program to another
• The destination address must be within -128 and +127
bytes from the current instruction address because an 8-
bit offset is used (28 = 256)

• Example:

GoBack: DEC A ;Decrement A

JNZ GoBack ;If A is not zero,
loop back
 Absolute Addressing
• Two instructions associated with this mode of addressing
are ACALL and AJMP instructions
• These are 2-byte instructions where the 11-bit absolute
address is specified as the operand
• The upper 5 bits of the 16-bit PC address are not
modified. The lower 11 bits are loaded from this
instruction. So, the branch address must be within the
current 2K byte page of program memory (211 = 2048)

• Example:
ACALL PORT_INIT ;PORT_INIT should be
;located within 2k bytes.

PORT_INIT: MOV P0, #0FH ;PORT_INIT subroutine

 Long Addressing
• This mode of addressing is used with the LCALL
and LJMP instructions
• It is a 3-byte instruction and the last 2 bytes
specify a 16-bit destination location where the
program branches
• It allows use of the full 64 K code space
• The program will always branch to the same
location no matter where the program was
previously
• Example:
LCALL TIMER_INIT ;TIMER_INIT address
(16-bits ;long) is
specified as the ;operand;
In C, this will be a ;function
call: Timer_Init().
TIMER_INIT: ORL TMOD,#01H ;TIMER_INIT subroutine
 Indexed Addressing
• The Indexed addressing is useful when there is a need to retrieve
data from a look-up table
• A 16-bit register (data pointer) holds the base address and the
accumulator holds an 8-bit displacement or index value
• The sum of these two registers forms the effective address for a
JMP or MOVC instruction

• Example:
MOV A,#08H ;Offset from table start
MOV DPTR,#01F00H ;Table start address
MOVC A,@A+DPTR ;Gets target value from the table
;start address + offset
and puts it ;in A.
• After the execution of the above instructions, the program will
branch to address 1F08H (1F00H+08H) and transfer into the
accumulator the data byte retrieved from that location (from the
look-up table)