Scribd
Upload
7 views

Ahb Protocol

The AHB (Advanced High-performance Bus) protocol is designed for high-performance, synthesizable systems, facilitating communication between Managers and Subordinates with features like burst transfers and configurable bus widths. It includes components such as a Decoder, Multiplexor, and interconnect logic to manage address decoding and data routing. Transfers can be classified into four types: IDLE, BUSY, NONSEQUENTIAL, and SEQUENTIAL, each serving specific operational purposes in data transfer management.

Uploaded by

koribillitejaswini
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
7 views

Ahb Protocol

The AHB (Advanced High-performance Bus) protocol is designed for high-performance, synthesizable systems, facilitating communication between Managers and Subordinates with features like burst transfers and configurable bus widths. It includes components such as a Decoder, Multiplexor, and interconnect logic to manage address decoding and data routing. Transfers can be classified into four types: IDLE, BUSY, NONSEQUENTIAL, and SEQUENTIAL, each serving specific operational purposes in data transfer management.

Uploaded by

koribillitejaswini
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 18

AHB PROTOCOL

Advanced High-performance Bus


Contents

• Introduction About the protocol


• AHB block diagram
• Signal descriptions
• Transfers
• Transfer types
Introduction About the protocol

AMBA AHB is a bus interface suitable for high-performance synthesizable designs.


It defines the interface between components, such as Managers, interconnects, and Subordinates.
AMBA AHB implements the features required for high-performance, high clock frequency systems
including:

• Burst transfers
• Single clock-edge operation
• Non-tristate implementation
• Configurable data bus widths
• Configurable address bus widths

The most common AHB Subordinates are internal memory devices, external memory interfaces, and high-
bandwidth peripherals
AHB block diagram
single Manager AHB system design with the AHB
Manager and three AHB Subordinates. The bus
interconnect logic consists of one address decoder and
a Subordinate-to-Manager multiplexor. The decoder
monitors the address from the Manager during the
address phase so that the appropriate Subordinate is
selected during the data phase of a transfer. The
multiplexor routes the corresponding Subordinate
output data back to the Manager.

AHB also supports multi-Manager designs by the use


of an interconnect component that provides arbitration
and routing signals from different Managers to the
appropriate Subordinates.
AHB block diagram

Manager:
A Manager provides address and control information to initiate read and write operations.
AHB block diagram

Subordinate:

A Subordinate responds to transfers initiated by


Managers in the system. The Subordinate uses
the HSELx select

signal from the decoder to control when it


responds to a bus transfer.
The Subordinate signals back to the Manager:
• The completion or extension of the bus transfer.
• The success or failure of the bus transfer.
AHB block diagram
Interconnect:

An interconnect component provides the connection between Managers and Subordinates in a system. A
single Manager system only requires the use of a Decoder and Multiplexor.

Decoder:
This component decodes the address of each transfer and provides a select signal for the Subordinate
that is involved in the transfer. It also provides a control signal to the multiplexor.

Multiplexor:
A Subordinate-to-Manager multiplexor is required to multiplex the read data bus and response signals
from the Subordinates to the Manager. The decoder provides control for the multiplexor.
Signal Descriptions
HCLK - The bus clock times all bus transfers. All signal timings are related to the rising edge of HCLK.
HRESETn - The bus reset signal is active LOW and resets the system and the bus. This is the only
active LOW signal.
Manager signals:
HADDR - The byte address of the transfer. ADDR_WIDTH is recommended to be between 10 and 64.
HBURST – Indicates how many transfers are in the burst and how the address increments. HBURST_WIDTH must be 0 or 3.
HMASTLOCK – Indicates that the current transfer is part of a locked sequence. It has the same timing as the address and
control signals.
HPROT – Protection control signal, which provides information about the access type.
HSIZE – Indicates the size of the transfer
HNONSEC – Indicates whether the transfer is Non-secure or Secure.
HEXCL – Indicates whether the transfer is part of an Exclusive Access sequence.
HMASTER - Manager identifier. Generated by a Manager if it has multiple Exclusive capable threads.
Signal Descriptions
HTRANS - Indicates the transfer type. This can be: IDLE , BUSY, NONSEQUENTIAL, SEQUENTIAL
HWDATA - Transfers data from the Manager to the Subordinates during write operations.
HWSTRB - Write strobes. Deasserted to indicate when active write data byte lanes do not contain valid
data.
HWRITE – Indicates the transfer direction.
Subordinate Signals:

HRDATA – Indicates that the current transfer is part of a locked sequence. It has the same timing as the address and control
signals.
HREADYOUT – When HIGH, the HREADYOUT signal indicates that a transfer has finished on the bus.
HRESP – The transfer response provides the Manager with additional information on the status of a transfer.
HEXOKAY – Exclusive Okay. Indicates the success or failure of an Exclusive Transfer.
Decoder signals

HSELxa - Each Subordinate has its own select signal HSELx and this signal indicates that the current transfer is intended for
the selected Subordinate.
Multiplexor signals:

HRDATA - Read data bus, selected by the decoder


HREADY - When HIGH, the HREADY signal indicates to the Manager and all Subordinates, that the
previous transfer is complete.
HRESP – Transfer response, selected by the decoder
HEXOKAY – Exclusive okay, selected by the decoder.
Transfers
Basic transfers
A transfer consists of two phases:
Address: Lasts for a single HCLK cycle unless it is extended by the previous bus transfer.
Data: Might require several HCLK cycles. Use the HREADY signal to control the number of clock
cycles required to complete the transfer.

Read Transfer
Transfers

Write Transfer
Transfers

Read transfer with two wait states


Transfers

Write transfer with two wait states


Transfers

Multiple Transfers
Transfer Types
The transfers that can be classified into one of four types, as controlled by HTRANS[1:0]

HTRANS[1:0] Type Description


0b00 IDLE Indicates that no data transfer is
required. A Manager uses an IDLE
transfer when it does not want to
perform a data transfer.

0b01 BUSY The BUSY transfer type enables


Managers to insert idle cycles in the
middle of a burst. This transfer type
indicates that the Manager is
continuing with a burst but the next
transfer cannot take place
immediately.
Transfer Types

HTRANS[1:0] Type Description


0b10 NONSEQ Indicates a single transfer or the
first transfer of a burst. The address
and control signals are unrelated to
the previous transfer. Single
transfers on the bus are treated as
bursts of length one and therefore
the transfer type is
NONSEQUENTIAL.
0b11 SEQ The remaining transfers in a burst
are SEQUENTIAL and the address is
related to the previous transfer.
Transfer Types

Transfer type examples

You might also like