3.

Logic Gates and Logic Families

Discrete Realization of Logic Gates

 Digital ICs are often categorized according to the complexity of their

circuits, as measured by the number of logic gates in a single package.

 Small‐scale integration (SSI) devices contain several independent gates in a single
package. The number of gates is usually fewer than 10 and is limited by the
number of pins available in the IC.
 Medium‐scale integration (MSI) devices have a complexity of approximately 10 to
1,000 gates in a single package. MSI digital functions are introduced in Chapters
ahead as decoders, adders, and multiplexers, registers and counters.
 Large‐scale integration (LSI) devices contain thousands of gates in a single
package. They include digital systems such as processors, memory chips, and
programmable logic.
 Very large‐scale integration (VLSI) devices now contain millions of gates within a
single package. Examples are large memory arrays and complex microcomputer
chips.
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  Digital integrated circuits are classified not only by their
complexity or logical operation, but also by the specific
circuit technology to which they belong. The circuit
technology is referred to as a digital logic family.

 Many different logic families of digital integrated circuits

have been introduced commercially. The following are the
most popular:

• TTL transistor–transistor logic;

• ECL emitter‐coupled logic;
• MOS metal‐oxide semiconductor;
• CMOS complementary metal‐oxide
semiconductor.

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  Transistor Switches
 MOSFET (metal oxide semiconductor field-effect
transistor) is used for implementing a simple switch.
• Two different types of MOSFETs
- NMOS: n-channel MOSFET
- PMOS: p-channel MOSFET

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 NMOS:
- Turned on when
gate terminal is
High.
- The drain is
pulled down to
ground.

PMOS:
- Turned on
when the gate
terminal is Low.
- The
drain is
4 pulled up to
V
NMOS Logic Gates
 The earlier schemes for building logic gates with MOSFETs.

NOT gate

 When Vx = 0 V, the NMOS transistor is

turned off. No current flows through the
resistor R, and Vf = 5 V.

 When Vx = 5 V, the transistor is turned on

and pulls Vf to a low voltage level.

Truthxtable:f
0 1
1 0

5
 NAND gate

 If Vx1= Vx2= 5 V, both transistors will

be on and Vf will be close to 0 V.

 But if either Vx1 or Vx2 is 0, then no

current will flow through the series-

connected transistors and Vf will be
pulled up to 5 V.

x x f
Truth
1
table:
2

0 0 1
0 1 1
1 0 1
1 1 0

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 NOR gate

 If either Vx1= 5 V or Vx2= 5 V,

then Vf will be close to 0 V.

 Only if both Vx1 and Vx2 are 0 will

Vf be pulled up to 5 V.

Truth table:

x1 x2 f
0 0 1
0 1 0
1 0 0
1 1 0

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AND gate OR gate

Truth table:
x1 x2 f
0 0 0
0 1 0 Truth table:
1 0 0 x1 x2 f
1 1 1 0 0 0
0 1 1
1 0 1
1 1 1
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CMOS Logic Gates
 CMOS circuits are introduced later to PMOS and NMOS
circuits
 CMOS: Complementary MOSFET.
- Combines NMOS and PMOS.
 pull-up network (PUN) is
built using PMOS transistors
 Pull-down network (PDN) is
build using NMOS.
 Either the PDN pulls Vf down
to Gnd or the PUN pulls Vf up
to VDD.

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  The categories of CMOS in terms of the dc supply voltages
are the 5V CMOS, the 3.3V CMOS, the 2.5V CMOS, and the
1.8V CMOS.
 The series within the CMOS family are designated by the
prefix 74 (commercial grade) or 54 (military grade)
followed by a letter or letters that indicate the series and
then a number that indicates the type of logic device.
 The basic CMOS series for the 5V category and their
designations include
 74HC and 74HCT – High-speed CMOS (the “T” indicates
TTL compatibility)
 74AC and 74ACT – Advanced CMOS
 74AHC and 74AHCT – Advanced High-speed CMOS

 The basic CMOS series for the 3.3V category and their
designations include
 74LVC – Low-voltage CMOS
 74ALVC – Advanced low-voltage CMOS
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 Input and output logic level (5V CMOS)

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 NOT gate

 When Vx = 0 V, transistor T2 is off and

transistor T1 is on. This makes Vf = 5 V, and

since T2 is off, no current flows through the
transistors.
 When Vx = 5 V, T2 is on and T1 is off. Thus

Vf = 0 V, and no current flows because T1

is off.
x T1 T2 f

Truth0 table:
O Of 1
n f
1 Of O 0
f n

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 NAND gate

 Under static conditions no path

exists for current flow from VDD to
Gnd.

Truth table and transistor

states: x x T1 T2 T3 T4 f
1 2

0 0 on on of of 1
f f
0 1 on of of on 1
f f
1 0 of on on of 1
f f
1 1 of of on on 0
f f

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 NOR gate

 The circuit for the NOR gate is

derived from the logic expression
that defines the NOR operation

Truth table and transistor state:

x x T1 T2 T3 T4 f
1 2

0 0 on on of of 1
f f
0 1 on of of on 0
f f
1 0 of on on of 0
f f
1 1 of of on on 0
f f
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 AND gate
- Built by connecting a NAND OR gate
gate to - Constructed with a NOR gate
an inverter. followed by a NOT gate.

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