Department of

Computer
Engineering
Unit-2
Basic Computer Organization Computer
Organization and
and Design Architecture-
01CE1402

Prof. Ashish Bhalodia

  Instruction codes
 Computer registers
 Computer instructions
 Timing and Control
 Instruction cycle
Outline  Memory-Reference Instructions
 Input- output and interrupt
 Complete description
 Design of Basic Computer
 Design of Accumulator Logic
  Program
 A program is a set of instructions that specify the
operations, operands and the sequence by which
processing has to occur.
 Computer Instruction
Instruction  A computer instruction is a binary code that specifies

Codes a sequence of microoperations for the computer.

 The computer reads each instruction from memory
and places it in a control register.
 The control then interprets the binary code of the
instruction and proceeds to execute it by issuing a
sequence of microoperations.
  Instruction Code
 An instruction code is a group of bits that instruct the
computer to perform a specific operation.
 Example Unique Binary
code is
assigned to
Instruction ADD 1547 every OpCode

Codes  Operation Code (Opcode)

 The operation code of an instruction is a group of bits that
define such operations as add, subtract, multiply, shift, and
complement.
 The number of bits required for the operation code of an
instruction depends on the total number of operations
available in the computer.
 The operation code must consist of at least n bits for a
given 2n (or less) distinct operations.
 Memory
4096 x 16

1 1 1 0
5 2 1 Instructions
Stored Opcode Address
(program)
Program Instruction
Format
Organizatio 1 0 Operand
n 5
Binary Operand (data)

Processor
Register
(accumulator or
AC)
  The simplest way to organize a computer is to
have one processor register(AC) and an
instruction code format with two parts.
 The first part specifies the operation (opcode) to
Stored
be performed and the second specifies an
Program
address (operand).
Organizatio  The memory address tells the control where to
n find an operand in memory.
 This operand is read from memory and used as
the data to be operated on together with the
data stored in the processor register.
  Instructions are stored in one section of memory
and data in another.
 For a memory unit with 4096 words, we need 12
bits to specify an address since 212 = 4096.
Stored
 If we store each instruction code in one 16-bit
Program
memory word, we have available four bits for
Organizatio
operation code (opcode) to specify one out of 16
n possible operations, and 12 bits to specify the
address of an operand.
  The control reads a 16-bit instruction from the
program portion of memory.
 It uses the 12-bit address part of the instruction
to read a 16-bit operand from the data portion
Stored
of memory.
Program  It then executes the operation specified by the
Organizatio
operation code.
n
 Instruction Format
1 1 1 1 0
5 4Opcod
2 1
I Address
e
Instruction
format of
basic
computer 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 1
Add Instruction – ADD 457
 Memory Memory
AD AD
2 0 457 3 1 300
D D
2 5

300 1350
Direct &
45 Operand
Indirect 7 135 Operand
Addressing 0
of Memory
+ +

AC AC

Direct Address Indirect Address

  If the second part of an instruction format
specifies the address of an operand, the
instruction is said to have a direct address.
 In Indirect address, the bits in the second part
Direct &
of the instruction designate an address of a
Indirect
memory word in which the address of the
Addressing
operand is found.
of Memory
  One bit of the instruction code can be used to
distinguish between a direct and an indirect
address.
 It consists of a 3-bit operation code, a 12-bit
Direct &
address, and an indirect address mode bit
Indirect
designated by I.
Addressing  The mode bit is 0 for a direct address and 1 for
of Memory an indirect address.
 1 1 1 1 0
5 4 2 1
2 0 ADD 457
2

 A direct address instruction is placed at address

Direct &
22 in memory.
Indirect  The I bit is 0, so the instruction is recognized as
Addressing a direct address instruction.
of Memory  The opcode specifies an ADD instruction, and
the address part is the binary equivalent of 457.
 The control finds the operand in memory at
address 457 and adds it to the content of AC.
 1 1 1 1 0
5 4 2 1
3 1 ADD 300
5

 The instruction in address 35 has a mode bit I =

Direct &
1, recognized as an indirect address instruction.
Indirect  The address part is the binary equivalent of 300.
Addressing  The control goes to address 300 to find the
of Memory address of the operand.
 The address of the operand in this case is 1350.
 The operand found in address 1350 is then
added to the content of AC.
  The indirect address instruction needs two
references to memory to fetch an operand.
 The first reference is needed to read the
address of the operand.
Direct &
 Second reference is for the operand itself.
Indirect  The memory word that holds the address of the
Addressing
operand in an indirect address instruction is
of Memory used as a pointer to an array of data.
 1 0
1 Program Counter(12)
PC Holds address of instruction
1 0
1 Address Register(12)
AR Holds address for memory
Computer 1 0
Instruction Register(16)
Registers 5
IR Holds instruction code
1 0
5 Temporary Register(16)
TR Holds temporary data
1 0
5 Data Register(16)
DR Holds memory operand
 1 0
5 Accumulator(16)
AC Processor Register
7 0
Output Register(8)
OUTR Holds output character
Computer 7 0
Registers Input Register(8)
INPR Holds input character

Memory
4096 words
16 bits per word
  Common bus

Common
bus system
of basic
computer
 S2
S1 Bus
Memory S0
4096 x 16 7
Addres
Writ Read s
e AR 1
LD INR CL
PC R 2
LD INR CL
DR R 3
LD INR CL
Adder E R
& AC 4
Logic
LD INR CL
R
INPR

IR 5
LD
TR 6
LD INR CL
OUTR R
Clock
LD
 1. Memory Reference Instruction
1 1 1 1 0
5 4Opcod
2 1
1 Address
e

Types of
Computer 2. Register Reference Instruction
Instructions 1 1
5 4
1
3
1 1
2 1
0
0 1 1 1 Register Operation

3. Input – Output Instruction

1 1 1 1 1 0
5 4 3 2 1
1 1 1 1 I/O Operation
 1. Memory Reference Instruction
1 1 1 1 0
5 4Opcod
2 1
I Address
e

0
1 0
1 0
1 0
1 Address
Types of
Computer 0xxx 8xxx ANDAND the content of memory to A
Instructions 1xxx 9xxx ADDAdd the content of memory to A
2xxx Axxx LDA Load memory word to AC
3xxx Bxxx STAStore content of AC in memory
4xxx Cxxx BUN Branch unconditionally
5xxx Dxxx BSABranch and save return address
6xxx Exxx ISZ Increment and skip if zero
 2. Register Reference Instruction
1 1 1 1 1 0
5 4 3 2 1
0 1 1 1 Register Operation

0 1 1 1 0 1
1 0 0 0
1 1 0 0
1 1 0
1 0 0 0 0 0
Types of
Computer 7800 CLA Clear AC
Instructions 7400 CLE Clear E
7200 CMA Complement AC
7100 CME Complement E
7080 CIR Circulate right AC and E
7040 CIL Circulate left AC and E
7020 INC Increment AC
 2. Register Reference Instruction
1 1 1 1 1 0
5 4 3 2 1
0 1 1 1 Register Operation

0 1 1 1 0 0 0 0 0 0 0 1
0 0 0
1 1 0
1 0
1
Types of
Computer 7010 SPASkip next instruction if AC is positive
Instructions 7008 SNASkip next instruction if AC is negative
7004 SZASkip next instruction if AC is zero
7002 SZESkip next instruction if E is zero
7001 HLT Halt computer
 3. Input – Output Instruction
1 1 1 1 1 0
5 4 3 2 1
1 1 1 1 I/O Operation

1 1 1 1 1
0 0 0
1 1 0
1 0
1 0
1 0 0 0 0 0 0
Types of
Computer F800 INP Input character to AC
Instructions F400 OUTOutput character from AC
F200 SKI Skip on input flag
F100 SKO Skip on output flag
F080 ION Interrupt on
F040 IOF Interrupt off
  Instruction set is said to be complete if it
includes sufficient number of instructions in
each of the following categories:
1. Arithmetic, logical and shift instructions
Instruction 2. Instructions for moving information to and from
Set memory and processor registers
Completene 3. Program control instructions together with

ss instructions that check status conditions

4. Input and output instructions
 0 0 0 1 010001010111
Instruction
Register Other
1 inputs
14 13 12 11 - 0
5
0 0 0 1
3x8
Decoder
Control Unit 7 6 5 4 3 2 Contro
D Control
of Basic I
1 0
D D
0
Logic
l O/p

Computer 1 7
Gates
T1
T0
5
15 14 ... 2
1 0 4 x 16
Decoder

4-bit sequence Increment

Clear
counter (SC) Cloc(INR)
(CLR)
k
  Components of Control unit are
1. Two decoders
2. A sequence counter
3. Control logic gates
 An instruction read from memory is placed in the
instruction register (IR).
Control Unit  In control unit the IR is divided into three parts: I bit,
the operation code (12-14)bit, and bits 0 through 11.
 The operation code in bits 12 through 14 are
decoded with a 3 x 8 decoder.
 Bit-15 of the instruction is transferred to a flip-flop
designated by the symbol I.
  The eight outputs of the decoder are designated by
the symbols D0 through D7.
 Bits 0 through 11 are applied to the control logic gates.
 The 4‐bit sequence counter can count in binary from 0
through 15. The outputs of counter are decoded into
16 timing signals T0 through T15.
Control Unit  The sequence counter SC can be incremented or
cleared synchronously.
 Most of the time, the counter is incremented to provide
the sequence of timing signals out of 4 X 16 decoder.
 Once in awhile, the counter is cleared to 0, causing the
next timing signal to be T0.
  As an example, consider the case where SC is incremented to provide
timing signals T0, T1, T2, T3 and T4 in sequence. At time T4, SC is cleared to
0 if decoder output D3 is active. This is expressed symbolically by the
statement
D3T4: SC ← 0
 Initially, the CLR input of SC is active.
 The first positive transition of the clock clears SC to 0, which in turn

Control Unit 
activates the timing T0 out of the decoder.
T0 is active during one clock cycle.
 The positive clock transition labeled T0 in the diagram will trigger only
those registers whose control inputs are connected to timing signal T0.
 SC is incremented with every positive clock transition, unless its CLR input
is active.
 This procedures the sequence of timing signals T0, T1, T2, T3 and T4, and so
on. If SC is not cleared, the timing signals will continue with T5, T6, up to
T15 and back to T0.
 𝑇0 𝑇1 𝑇2 𝑇3 𝑇4 𝑇5
Clock

𝑇0

𝑇1
Timing Cycle

←0
𝑇2
for D3T4: SC
𝑇3
𝑇4

𝐷3
CL
R

SC
  The last three waveforms shows how SC is cleared when
D3T4 = 1.
 Output D3 from the operation decoder becomes active at
the end of timing signal T2.
 When timing signal T4 becomes active, the output of the
AND gate that implements the control function D 3T4
Control Unit becomes active.
 This signal is applied to the CLR input of SC.
 On the next positive clock transition the counter is cleared
to 0.
 This causes the timing signal T0 to become active instead of
T5 that would have been active if SC were incremented
instead of cleared.
  Hardwired Control
 The control logic is implemented with gates, flips-
flops, decoders and other digital circuits.
 It can be optimized to produce a fast mode of
operation.
Control  It requires changes in the wiring among the various
Organizatio components if the design has to be modified or
n changed.
 Microprogrammed Control
 The control information is stored in a control memory.
 The control memory is programmed to initiate the
required sequence of micro-operations.
 Any required changes or modifications can be done by
updating the microprogram in control memory.
  A program residing in the memory unit of the
computer consists of a sequence of instructions. In
the basic computer each instruction cycle consists
of the following phases:
1. Fetch an instruction from memory.
Instruction 2. Decode the instruction.

Cycle 3. Read the effective address from memory if the instruction

has an indirect address.
4. Execute the instruction.
 After step 4, the control goes back to step 1 to
fetch, decode and execute the next instruction.
 This process continues unless a HALT instruction is
encountered.
  Fetch & Decode
 PC is loaded with the address of the first instruction in
the program.
 The micro-operations for fetch and decode phases are

𝑇 as follows:
: 𝐴𝑅←
0 𝑃𝐶
Instruction 𝑇 1 : 𝐼𝑅 ← 𝑀 [ 𝐴𝑅 ] , 𝑃𝐶 ← 𝑃𝐶+1
Cycle 𝑇 2 : 𝐷 0 , … , 𝐷 7 ← 𝐷𝑒𝑐𝑜𝑑𝑒 𝐼𝑅 ( 12− 14 ) , 𝐴𝑅← 𝐼𝑅 ( 0 −11 ) , 𝐼 ← 𝐼𝑅(15)
  Determine the type of instruction
 During time , the control unit determines the type of
instruction i.e. Memory reference, Register reference
or Input-Output instruction.
 If then instruction must be register reference or input-

Instruction output else memory reference instruction.

 Instruction Cycle Flowchart
Cycle
 SC ← 0
Start

𝑇0
AR ← PC

IR ← M[AR], PC ←
𝑇1
PC + 1
𝑇2
Decode operation code in

AR ← IR(0-11), I ← IR(15)
IR(12-14)

(Register or I/O) = 1 D = 0 (Memory-reference)

7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I

AR ←
Execute𝑇3 Execute
𝑇3 𝑇3 𝑇3
input- Nothing
register- M[AR
output
reference ]
instructio
SC ← 0
instruction
SC ← 0
n
Execute
memory-
reference

SC ← 0
instruction
 D7I’T3 = r (common to all register reference instructions)

CLA rB11 AC ← 0
IR(i) = Bi [bit in IR(0-11) that specifies the operation]
Clear AC
E←0
AC ← AC’
CLE rB10 Clear E

E ← E’
CMA rB9 Complement AC
Register
rB7 AC ← shr AC, AC(15) ← E, E ← AC(0)Circulate right
CME rB8 Complement E

Reference
rB6 AC ← shl AC, AC(0) ← E, E ← AC(15)Circulate left
CIR

rB5 AC ← AC + 1
CIL
Instruction INC Increment AC
SPA rB4 If (AC(15) = 0) then (PC ← PC + 1) Skip if AC is positive
SNA rB3 If (AC(15) = 1) then (PC ← PC + 1) Skip if AC is negative
If (AC = 0) then (PC ← PC + 1)
If (E = 0) then (PC ← PC + 1)
SZA rB2 Skip if AC is zero
SZE rB1 Skip if E is zero
HLT rB0 S ← 0 (S is a start-stop flip-flop) Halt Computer
 1. AND: AND to AC
This is an instruction that performs the AND
logic operation on pairs of bits in AC and the
memory word specified by the effective
Memory address. The result of the operation is
Reference transferred to AC.
D T : DRM[AR]
0 4
Instructions D0T5: AC  AC  DR, SC  0
 2. ADD: ADD to AC
This instruction adds the content of the
memory word specified by the effective address
to the value of AC. The sum is transferred into
Memory AC and the output carry Cout is transferred to
Reference the E (extended accumulator) flip-flop.
D1T4: DRM[AR]
Instructions
D1T5: AC  AC + DR, E  Cout, SC  0
 3. LDA: Load to AC
This instruction transfers the memory word
specified by the effective address to AC.

Memory D2T4: DRM[AR]

Reference D2T5: AC  DR, SC  0
Instructions
 4. STA: Store AC
This instruction stores the content of AC into
the memory word specified by the effective
address.
Memory D3T4: M[AR]  AC, SC  0
Reference
Instructions
 5. BUN: Branch Unconditionally
This instruction transfers the program to
instruction specified by the effective address.
The BUN instruction allows the programmer to
Memory specify an instruction out of sequence and the
Reference program branches (or jumps) unconditionally.
Instructions
D4T4: PC  AR, SC  0
 6. BSA: Branch and Save Return Address
This instruction is useful for branching to a
portion of the program called a subroutine or
procedure. When executed, the BSA instruction
Memory stores the address of the next instruction in
Reference sequence (which is available in PC) into a
Instructions Dmemory
5T4: M[AR]  PC, AR  AR + 1
location specified by the effective
address.
D T : PC  AR, SC  0
5 5
 0 BSA 0 BSA
20 20
135 135
PC = 21 Next Instruction 21 Next Instruction

AR = 135 135 2
136 PC = 136 1

BSA Subroutine Subroutine

1 BUN 1 BUN
135 135
Memory, PC and AR at Memory and PC after
Time T4 execution

D5T4: M[135]  21, AR  135 + 1

D5T5: PC  136, SC  0
 7. ISZ: Increment and Skip if Zero
These instruction increments the word specified
by the effective address, and if the
incremented value is equal to 0, PC is
Memory incremented by 1. Since it is not possible to
Reference increment a word inside the memory, it is
Instructions necessary to read the word into DR, increment
DR,
D and store the word back into memory.
6T4: DR  M[AR]

D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC 
PC + 1),
SC  0
 Memory-reference instruction

AND ADD LDA STA

D 0T4 D 1T4 D 2T4 D 3T4

DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

Flowchart D 0T5
AC  AC /\ DR AC  AC + DR
D 1T5
AC  DR
D 2T5

for Memory
SC  0 E  Cout SC  0
SC  0

Reference BUN

D 4T4
BSA

D 5T4
ISZ

D 6T4

Instructions PC  AR
SC  0
M[AR]  PC
AR  AR + 1
DR  M[AR]

D 5T5 D 6T5

PC  AR DR  DR + 1
SC  0
D 6T6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
 Input-Output Serial Computer
terminal communicati registers and flip-
on interface flop
FGO =1
=0

Input- Printer
Receiver
OUTR
Output of Interface

basic
computer AC

Transmitter
Keyboard INPR
Interface

FGI =1
=0
  A computer can serve no useful purpose unless it
communicates with the external environment.
 To exhibit the most basic requirements for input and output
communication, we will use a terminal unit with a keyboard

Input- 
and printer.
The terminal sends and receives serial information and each
Output of quantity of information has eight bits of an alphanumeric
basic code.

computer  The serial information from the keyboard is shifted into the
input register INPR.
 The serial information for the printer is stored in the output
register OUTR.
 These two registers communicate with a communication
interface serially and with the AC in parallel.
  Initially, the input flag FGI is cleared to 0. When
a key is struck in the keyboard, an 8-bit
alphanumeric code is shifted into INPR and the
input flag FGI is set to 1.
Process of
 As long as the flag is set, the information in
input
INPR cannot be changed by striking another key.
information
The computer checks the flag bit; if it is 1, the
transfer information from INPR is transferred in parallel
into AC and FGI is cleared to 0.
 Once the flag is cleared, new information can be
shifted into INPR by striking another key.
  The output register OUTR works similarly but
the direction of information flow is reversed.
 Initially, the output flag FGO is set to 1. The
computer checks the flag bit; if it is 1, the
Process of information from AC is transferred in parallel to
outputting OUTR and FGO is cleared to 0. The output
information device accepts the coded information, prints the
corresponding character, and when the
operation is completed, it sets FGO to 1.
 The computer does not load a new character
into OUTR when FGO is 0 because this condition
indicates that the output device is in the
process of printing the character.
 D7IT3 = p (common to all input-output instructions)

pB11 AC(0-7) ← INPR, FGI ← 0

IR(i) = Bi [bit in IR(6-11) that specifies the operation]

pB10 OUTR ← AC(0-7), FGO ← 0

INP Input Character
OUT Output Character
SKI pB9 If (FGI = 1) then (PC ← PC + 1) Skip on input flag
If (FGO = 1) then (PC ← PC + 1)
Input- SKO pB8 Skip on output flag
Output IEN ← 1
IEN ← 0
ION pB7 Interrupt enable on
Instruction IOF pB6 Interrupt enable off
 Instruction cycle= 0 = 1Interrupt cycle
R

Store return
Fetch & Decode address in
instruction
M[0] ← PC
location 0

Interrupt Execute
instructio
IE =0
N Branch to
Cycle n
PC ← 1
=1 location 1
=1 FGI

IEN ← 0
=0

R←0
=1 FGO

R←
=0
1
  The interrupt cycle is a hardware
implementation of a branch and save return
address operation.
 An interrupt flip-flop R is included in the
computer.
Interrupt  When R = 0, the computer goes through an
Cycle
instruction cycle.
  During the execute phase of the instruction cycle IEN is
checked by the control.
 If it is 0, it indicates that the programmer does not want to
use the interrupt, so control continues with the next
instruction cycle.
 If IEN is 1, control checks the flag bits.
Interrupt  If both flags are 0, it indicates that neither the input nor the
Cycle output registers are ready for transfer of information.
 In this case, control continues with the next instruction
cycle. If either flag is set to 1 while IEN = 1, flip-flop R is set
to 1.
 At the end of the execute phase, control checks the value of
R, and if it is equal to 1, it goes to an interrupt cycle instead
of an instruction cycle.
  The flip-flop is set to 1 if IEN = 1 and either FGI or
FGO are equal to 1. This can happen with any
clock transition except when timing signals T0, T1
Register or T2 are active.
transfer  The condition for setting flip-flop R= 1 can be
statements expressed with the following register transfer
for Interrupt statement:
cycle T0T1T2  (IEN) (FGI + FGO): R  1
 The symbol + between FGI and FGO in the control
function designates a logic OR operation. This is
AND with IEN and T0T1 T2.
  The fetch and decode phases of the instruction
cycle must be modified and Replace T0, T1, T2
with R'T0, R'T1, R'T2
Register  Therefore the interrupt cycle statements are :
transfer RT0 : AR  0, TR  PC
statements RT1 : M[AR]  TR, PC  0
for Interrupt
RT2 : PC  PC + 1, IEN  0, R  0, SC
cycle
0
  During the first timing signal AR is cleared to 0,
and the content of PC is transferred to the
temporary register TR.
Register  With the second timing signal, the return
transfer address is stored in memory at location 0 and
statements PC is cleared to 0.
for Interrupt  The third timing signal increments PC to 1,
cycle clears IEN and R, and control goes back to T0 by
clearing SC to 0.
 The beginning of the next instruction cycle has
the condition RT0 and the content of PC is equal
to 1. The control then goes through an
 0 0 256
0 BUN 0 BUN
1 PC = 1
1120 1120
255 255
Demonstrati PC = 256
Main Program
256
Main Program
on of
Interrupt 1120 1120
Cycle I/O program I/O program

1 BUN 1 BUN
0 0
Before Interrupt After Interrupt
Complete
Computer
Description
(Micro-
operations)
Complete
Computer
Description
(Micro-
operations)
  Hardware Components of Basic Computer
A memory unit: 4096 x 16.
Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR,
and SC
Flip-Flops(Status): I, S, E, R, IEN, FGI, and FGO
Design of Decoders: a 3x8 Opcode decoder & a 4x16
Basic timing decoder
Computer Common bus: 16 bits
Adder and Logic circuit: Connected to AC
 Control Logic Gates:
Input Controls of the nine registers
Read and Write Controls of memory
Set, Clear, or Complement Controls of the flip-
flops
  Basic Computer

Design of
Basic
Computer
 SC ← 0, IEN ← 0, R ← 0
Start

(Instruction cycle) = 0 (Interrupt cycle) = 1

R

AR ← 0, TR ← 0
𝑅′𝑇0 𝑅𝑇
AR ← PC
PC

IR ← M[AR], PC ← M[AR] ← TR, PC

𝑅′𝑇1 𝑅𝑇 1
PC + 1 ←0

PC ← PC + 1,
𝑅′𝑇2 𝑅𝑇 2
IEN ← 0, R ← 0,
Decode operation code in

AR ← IR(0-11), I ← IR(15) SC ← 0
IR(12-14)

(Register or I/O) = 1
D = 0 (Memory-reference)
7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I

𝑇3
AR ← 3
𝑇3 𝑇 𝑇3
Execute Execute
Nothin
input- register- M[AR g
output reference ]

SC ← 0 SC ← 0
instruction instruction
Execute
memory-
reference

SC ← 0
instruction
  In order to design the logic associated with AC,
it is necessary to extract all the statements that
change the content of AC.
Design of
D0T5: AC ← AC ∧ DR, SC ← 0 AND with DR
Accumulato D1T5: AC ← AC + DR, SC ← 0 ADD with DR
r Unit D2T5: AC ← DR Transfer from DR
pB11: AC(0-7) ← INPR, FGI ← 0 Transfer from INPR
rB9: AC ← Complement
AC’
rB 7: AC ← shr AC, AC(15) ← E Shift right
rB6: AC ← shl AC, AC(0) ← Shift left
E
rB11: AC ← Clear
0 5: AC ← AC + 1
rB Increment
 Circuit associated
with AC
1
6 1 1
1 Adder and Accumulator
From 6 6
6 logic circuit register (AC) To
DR 8
From bus
Design of INPR

LD IN
Accumulato
CLR
R Cloc
k
r Logic Control gates
 Gate structure for controlling LD, INR and
CLR of AC
D AN
T D 1 1
0 5
6 AC 6
D AD From To bus
D Adder &
1
D D LD IN CLR
Logic Clock
Design of T5
2
p
R R

Accumulato B11
r
INP
R

r Logic B9 CM
A
SHR
B7
SHL
B6
INC
B5
CLR
B11
Thank You