Advanced

Computer Architecture
Processor Design control for Multi Cycle
Lecture Objective
 Break instructions into cycles
 Put cycle sequence together
 Control Signal groups and micro operations
 Control states and signal values
 Control State transitions
Multi Cycle Datapath

2
S
PC + 4 (28-31)

0
rs 21-25
2
rdad1 A

rddata1 1 1
PC 0 IR
rt 16-20
rdad2

ALU
adrs
1 B 3
rddata 0 rddata2 0
write
wrdata RES
rd 11-15 4 2
1 wrdata RF
MEM 1

00-15 0
DR
X
S

2
S
0
1
Break Instruction Execution into
Cycles: R-Class instructions
IR = Mem[PC]
Cycle 1
PC = PC + 4

A =RF[IR[25-21]
Cycle 2
B =RF[IR[20-16]

Cycle 3 Op depends
Res = A op B upon IR 5-0

Cycle 4 RF[IR[15-11]] = Res

Break Instruction Execution into
Cycles: sw instructions
IR = Mem[PC]
Cycle 1
PC = PC + 4

A =RF[IR[25-21]
Cycle 2 B =RF[IR[20-16]

Cycle 3 Res = A + sx(IR [15-0]

Cycle 4 MEM[Res] = B
Break Instruction Execution into
Cycles: lw instructions
IR = Mem[PC]
Cycle 1
PC = PC + 4

Cycle 2 A =RF[IR[25-21]

Cycle 3 Res = A + sx(IR [15-0]

Cycle 4 DR = MEM[Res]

Cycle 5 RF[IR[20-16]] = DR
Break Instruction Execution into
Cycles: beq instructions
IR = Mem[PC]
Cycle 1
PC = PC + 4

A =RF[IR[25-21]
Cycle 2 B = RF[IR[20-16]
Res = PC + s2(sx(IR[15-11]))

Cycle 3 if(A==B)PC= Res

Break Instruction Execution into
Cycles: j instructions
IR = Mem[PC]
Cycle 1
PC = PC + 4

Cycle 2 PC = PC[31-28] || s2(IR[25-0])

Why have we divided

execution of this
instructions into two
cycles ?
Recall… Delay for {j}

2
S
4
PC + 4 (28-31)
+

00-25 t+
max
tI
PC ad inst

IM
 Put Cycle Sequence
together
R-Class sw lw beq j

IR = Mem[PC] IR = Mem[PC] IR = Mem[PC] IR = Mem[PC]

IR = Mem[PC]
PC = PC + 4 PC = PC + 4 PC = PC + 4 PC = PC + 4
PC = PC + 4

A =RF[IR[25-21]
B = RF[IR[20-16]
A =RF[IR[25-21] A =RF[IR[25-21] A =RF[IR[25-21] PC = PC[31-
Res = PC + s2(sx(IR[15-
B =RF[IR[20-16] A =RF[IR[25-21] 28] ||
11]))
s2(IR[25-0])
Res = A + sx(IR [15-0]

Res = A + sx(IR [15-0]

Res = A op B if(A==B)PC= Res
DR = MEM[Res]

RF[IR[5-11]] =
MEM[Res] = B RF[IR[20-16]] = DR These can
Res
be merged
 After merging Fetch Cycle
IR =
Mem[PC]
PC = PC + 4

R-Class sw lw beq j

A =RF[IR[25-21]
B = RF[IR[20-16]
A =RF[IR[25-21] A =RF[IR[25-21] A =RF[IR[25-21] PC = PC[31-
Res = PC + s2(sx(IR[15-
B =RF[IR[20-16] B =RF[IR[20-16] 28] ||
11]))
s2(IR[25-0])
Res = A + sx(IR [15-0]

Res = A + sx(IR [15-0]

Res = A op B if(A==B)PC= Res
DR = MEM[Res]

RF[IR[5-11]] = Opcode is available

MEM[Res] = B RF[IR[20-16]] = DR
Res only second cycle
onwards.
Split from 3rd cycle
onwards after
decoding opcode
With a Common Decoding Cycle
IR =
Mem[PC]
PC = PC + 4

A =RF[IR[25-21]
B = RF[IR[20-16]
Res = PC + s2(sx(IR[15-11]))

R-Class sw lw beq j

PC =
PC[31-28]
Res = A op B Res = A + sx(IR [15-0] Res = A + sx(IR [15-0] if(A==B)PC= Res ||
s2(IR[25-
0])

RF[IR[5-11]] = DR = MEM[Res]
Res MEM[Res] = B

RF[IR[20-16]] = DR
lw, sw can split after third
cycle
IR =
Mem[PC]
PC = PC + 4

A =RF[IR[25-21]
B = RF[IR[20-16]
Res = PC + s2(sx(IR[15-11]))

R-Class sw/lw beq j

Res = A op B Res = A + sx(IR [15-0] if(A==B)PC= Res PC =

RF[IR[5-11]] =
Res MEM[Res] = B DR = MEM[Res]

RF[IR[20-16]] = DR
Control Signal in Multicycle DP

2
S
PC + 4 (28-31)

RW ASrc1

P Z
IorD MR MW AW 0
W
rs 21-25
2
rdad1 A Re
W
rddata1 1 1
PC 0 IR
rt 16-20
rdad2

ALU
adrs
1 B 3
rddata 0 rddata2 0
write
wrdata RES
rd 11-15 4 2
1 wrdata RF BW PSrc
DM 1
Rds OP
t
IW 00-15 0
DR
X
S

2
S
0 ASrc2
DW 1

M2
R
Micro operations and control
Signals – PC Group
PWu PWc
Micro operation
PSrc

PC = PC + 4 1
PCinc X 1

If (A==B) PC = Res 0
branch 1 0

PC = PC[31-28] ||s2(IR[25-0]) jmp1 X 2

default nop0 0 X

PW = PWu + Z .
PWc
Micro operations and control
Signals – Mem Group
MW MR IorD IW
Micro operation
DW

IR = Mem[PC] 0
fetch 1 0 1 0

Dr = Mem[Res] 0
m_rd 1 1 0 1

Mem[Res] = B 1
m_wr 0 1 0 0

default nop0 0 X 0 0
Micro operations and control
Signals – RF Group
Micro operation RW Rdst M2R AW BW

A = RF[IR[25-21]] 0
rs2A X X 1 0

B = RF[IR[20-16]] 0
rt2B X X 0 1

RF[IR[15-11]]=Res 1
res2rd X X 0 0

RF[IR[20-16]]= DR 1
mem2rt 1 0 0 0

default 0
nop X X 0 0
Micro operations and control
Signals – ALU Group
Micro operation opc Asrc1 Asrc2 ReW

PC = PC + 4 0
PCinc 0 1 0

Res = A op B 2
arith 1 0 1

Res = A + sx(IR[15-0]) 0
Maddr 1 2 1

Res = PC + s2(sx(IR[15-11]))Paddr
0 0 3 1

If (A == B) PC = Res branch
1 1 0 0

default nopX X X 0
 Control states and micro
operations
cs0
Fetch
PCinc

rs2A
cs1 rt2B
Paddr
R-Class sw/lw beq j

cs4
cs8 cs9

cs2 arith Maddr branch jmp

sw lw
cs3 res2rd m_wr m_rd cs6

cs5
mem2rt cs7
Control states and Signals
values PC grp Memgrp RF grp ALUgrp

cs0 PCinc fetch nop PCinc

cs1 nop nop rs2A,rs2B Paddr

cs2 nop nop nop arith

cs3 nop nop res2rd nop

cs4 nop nop nop Maddr

cs5 nop m_wr nop nop

cs6 nop m_rd nop nop
cs7 nop nop mem2r1 nop
cs8 Branch nop nop branch

cs9 Jump nop nop nop

Control states transitions
R-class sw lw beq jmp

cs0 cs1 cs1 cs1 cs1 cs1

cs1 cs2 cs4 cs4 cs8 cs9

cs2 cs3 x x x x

cs3 cs0 x x x x

cs4 x cs5 cs6 x x

cs5 x cs0 x x x
cs6 x x cs7 x x
cs7 x x cs0 x x
cs8 x x x cs0 x

cs9 x x x x cs0
Summary
 Instructions expressed as sequence of micro
operations
 Control signals and grouped
 Micro operations define values of control

signals of a group
 Control states associated with micro

operations
 Control states transitions depend upon

opcode