Advanced

Computer Architecture
Processor with single cycle
Previous lectures
 we saw that the performance of a machine was
determined by three key factors: instruction
count, clock cycle time, and clock cycles per
instruction (CPI).
 The compiler and the instruction set
architecture, which we examined in previous
lectures, determine the instruction count
required for a given program.
 However, both the clock cycle time and the
number of clock cycles per instruction are
determined by the implementation of the
processor.
Outlines of this Lecture
 Start with R class instruction
 Other instruction step by step
 Identify Control Signal
 Interconnect Datapath and Design
MIPS subset for
implementation
 Arithmetic Logic Instruction
◦ add, sub, and, or , slt
 Memory Reference Instruction
◦ lw,sw
 Control Flow Instruction
◦ j , beq
Common steps for every
instruction
 For every instruction, the first two steps are
identical:
1. Send the program counter (PC) to the
memory that contains the code and fetch
the instruction from that memory.
2. Read one or two registers, using fields of
the instruction to select the registers to
read. For the load word instruction, we need
to read only one register, but most other
instructions require that we read two
registers.
Datapath and Controller

Datapath

Status Signal Control Signal

Controller
Datapath for
add,sub,and,or,slt
 Fetch Instruction
 Address the register file
 Pass operands to ALU Action
Required
 Pass result to register file
 Increment PC

◦ Format add, $t0,$t1,$s2

PC ad inst

IM
Addressing the Register
File(RF)

rs 21-25
rdad1

rdad2 rddata1
rt 16-20
PC ad inst
wrad rddata2

IM wrdata
RF
Passing Operands to ALU

rs 21-25
rdad1

rdad2 rddata1
rt 16-20

ALU
PC ad inst
wrad rddata2

IM wrdata
RF
Passing the Results to RF

rs 21-25
rdad1

rdad2 rddata1
rt 16-20

ALU
PC ad inst rd 11-15
wrad rddata2

IM wrdata
RF
Incrementing PC
4
+

rs 21-25
rdad1

rdad2 rddata1
rt 16-20

ALU
PC ad inst rd 11-15
wrad rddata2

IM wrdata
RF
Load and Store Instruction
 Format : I

 Example: lw $t0, 32($s2)

35 18 9 32
op rs rt 16 bit Number
Adding “sw” instruction
4
+

rs 21-25
rdad1

PC rt 16-20
rddata1

ALU
ad inst rdad2 adrs rddata
rd 11-15 rddata2 0
wrad
IM wrdata
wrdata RF 1
DM

00-15
X
S
Adding “lw” instruction
4
+

rs 21-25
rdad1

PC rt 16-20
rddata1

ALU
ad inst rdad2 adrs rddata
1
rd 11-15
0 rddata2 0
wrad
IM wrdata
rd 11-15 0
1 wrdata RF 1
DM

00-15
X
S
Format of “beq”
Instruction
 Format : I

op rs rt 16 bit Number
Adding “beq” instruction
0
4
+

+
2
S
rs 21-25
rdad1

PC rt 16-20
rddata1

ALU
ad inst rdad2 adrs rddata
1
rd 11-15
0 rddata2 0
wrad
IM wrdata
rd 11-15 0
1 wrdata RF 1
DM

00-15
X
S
Format of jump Instruction
 Format :j

op 26 bit Number
Control Signals
00-25
1

2
S
0
4
0
+

+
PC+4 (28-31)

2
S
rs 21-25
rdad1

PC rt 16-20
rddata1

ALU
ad inst rdad2 adrs rddata
1
0 rddata2 0
wrad
IM wrdata
rd 11-15 0
1 wrdata RF 1
DM

00-15
X
S
Datapath + Control
JMP

00-25
1

2
S
0
4
0
+

+
PC+4 (28-31)

2
S
PCSource

Contro
26-31

l
Branch

Regwrite

rs 21-25
rdad1 MW
RegDst. zero

PC rt 16-20
rddata1 M2R

ALU
ad inst rdad2 ALU Src adrs rddata
1
0 rddata2 0
wrad
IM wrdata
rd 11-15 0
1 wrdata RF 1
DM
MW

control
ALU
00-15
X
S

00-05
Summary
 Processor Designed for {add, sub, and,
or, slt, lw, sw, beq}
 Step by step approach
 Started with {add,sub,and,or,slt}
 Added {sw,lw}, then added {beq,j}
 Identified control signal and connected to a

controller (black box)