Advanced

Computer Architecture
Processor Design Exception Handling
Lecture Outlines
 What are exceptions and interrupts
 Examples
 Handling Exceptions - basic ideas
 Modify our design to handle exceptions
 Exception handling in MIPS
What are exceptions
 Unusual events/conditions
◦ Source: Internal or External
◦ Synchronous or Asynchronous
◦ Intentional or unintentional
 Require change in flow of control
◦ Mechanism to alter the control flow
◦ Event identification and response to it
◦ Halt or resume original control flow
Terminology
Exception VS Interrupts
 Use both the term interchangeably
 MIPS: exception – internal as well as
external, interrupt – external
 Intel 80x86: interrupt - internal as well as

external, interrupt – external

 Power PC: exception – unusual event

interrupt – change in flow of control

Examples of Exeptions
*synchronous *asynchronous

Intentional Unintentional
Internal Invoke OS Access to privileged instruction,
function, Overflow/Underflow,
Undefined Instruction
Hardware malfunction
External I/O Device Mem Access exception,
Request Alignment Error,
Timeouts,
Power Down,
Hardware malfunction
How Exceptions are
handled
Uninterrupted Execution

Interrupt and
halt

Interrupt and resume

(vectored interrupt)

Interrupt and resume

(non-vectored)
Nested Interrupts
Checking for Exceptions MIPS

E W
IF D
X B

Undefined instruction
checked here
Overflow checked
here
Changes required in
Datapath
 Exception Program counter
◦ Saves PC of the instruction causing exception
◦ For resuming interrupted program
 Cause Register
◦ Records the cause of the exception
◦ 0: undefined instruction 1: arithmetic overflow
 Address of the exception handler/ISR
◦ C000 0000 in our case
◦ Multiple addresses for vectored interrupts
DP Modified for Exceptions C0000000

2
S
CW

PC + 4 (28-31) Int

RW ASrc1
Cause
3
P Z
IorD MR MW AW 0
W
2
rs 21-25 A Re
rdad1
W
rddata1 1 1
PC 0 IR
rt 16-20
rdad2

ALU
adrs
1 B 3 0
rddata 0 rddata2
write
wrdata RES
rd 11-15 4 2
1 wrdata RF BW PSrc
DM 1
Rds OP
t
IW 00-15 0 E
DR W
X
S

2
S
EPC
0 ASrc2
DW 1

M2
R
 Control states and micro
operations
cs0
Fetch
PCinc

rs2A
cs1 rt2B
Paddr
R-Class sw/lw beq j

cs9
cs4
cs8

cs2 arith Maddr branch jmp

sw lw
cs11
cs3 res2rd cs6
m_wr m_rd
cs10

OV OV cs5
mem2rt cs7
New Control States

OV else
cs10
EPC = PC – 4
EPC = PC – 4
cs11 Cause = 0
Cause = 1
PC =
PC =
C0000000
C0000000

ASRC = 0, ASRC2 = 01 , opc = 01 , ReW = 0

PWu = 1, PWc = 0, PSrc = 11
EW = 1
CW = 1
Int = 1 (for sc10) or int = 0 (for cs =11)
Other Issues
 Controlling Exception Handling
◦ Enable – disable
◦ Masking
◦ Priorities

 Saving Processor State

◦ Hardware
◦ Software

 Return from Exception

Exception handling in MIPS
Co-porcessor 0

 BadVAddr register 8
◦ Mem address at which reference occurred
 Status register 12
◦ Interrupt mask and enable bits
 Cause register 13
◦ Exception type and pending interrupts
 EPC register 14
◦ Address of instruction that caused exception
Summary
 Definitions and Examples
 Checking for exceptions and altering flow of

control
 Design Enhancements for exceptions
 Co-processor 0 in MIPS