UNIT-5 SEQUENTIAL CIRCUIT

TOPICS:
• DEFINITION OF SEQUENTIAL CIRCUIT
• ADVANTAGES OF SEQUENTIAL CIRCUIT
• DISADVANTAGES OF SEQUENTIAL CIRCUIT
• TYPES
• CLOCK AND TRIGGER
• LATCHES
• TYPES
• FLIP PLOPS
• TYPES
• CONVERSION OF FLIP FLOPS
• REGISTERS
• TYPES
• COUNTERS
Sequential Circuit :
• Sequential circuits are digital circuits that store and use
previous state information to determine their next state.
• They are commonly used in digital systems to implement state
machines, timers, counters, and memory elements and are
essential components in digital systems design.
• The memory elements in sequential circuits can be
implemented using flip-flops, which are circuits that store
binary values and maintain their state even when the inputs
change.
• Sequential circuit is a combinational logic circuit
that consists of inputs variable (X), logic gates
(Computational circuit), and output variable (Z).
• A combinational circuit produces an output based on input
variables only, but a sequential circuit produces an output
based on current input and previous output variables.
• That means sequential circuits include memory elements that
are capable of storing binary information.
• That binary information defines the state of the sequential
circuit at that time.
• A latch capable of storing one bit of information.
As shown in the figure, there are two types of input to the combinational logic :
1.External inputs which are not controlled by the circuit.

2.Internal inputs, which are a function of a previous output state.

Types of Sequential Circuits

There are two types of sequential circuits

• Asynchronous Sequential Circuit

• Synchronous Sequential Circuit

Asynchronous Sequential Circuit :
• These circuits do not use a clock signal but uses the pulses
of the inputs.
• These circuits are faster than synchronous sequential circuits
because there is clock pulse and change their state
immediately when there is a change in the input signal.
• We use asynchronous sequential circuits when speed of
operation is important and independent of internal clock
pulse.

• But these circuits are more difficult to design

and their output is uncertain.
 • Synchronous Sequential Circuit :These circuits uses clock
signal and level inputs (or pulsed) (with restrictions on pulse
width and circuit propagation).
• The output pulse is the same duration as the clock pulse for the
clocked sequential circuits. Since they wait for the next clock
pulse to arrive to perform the next operation, so these circuits
are bit slower compared to asynchronous.
• Level output changes state at the start of an input pulse and
remains in that until the next input or clock pulse.
• We use synchronous sequential circuit in synchronous
counters, flip flops, and in the design of MOORE-MEALY state
management machines. We use sequential circuits to design
Counters, Registers, RAM, MOORE/MEALY Machine and other
state retaining machines.
Advantages of Sequential Circuits
1.Memory: Sequential circuits have the ability to store binary
values, which makes them ideal for applications that require
memory elements, such as timers and counters.
2.Timing: Sequential circuits are commonly used to implement
timing and synchronization in digital systems , making them
essential for real-time control applications.
3.State machine implementation: Sequential circuits can be
used to implement state machines, which are useful for
controlling complex digital systems and ensuring that they
operate as intended.
4.Error detection: Sequential circuits can be designed to
detect errors in digital systems and respond accordingly,
improving the reliability of digital systems.
Disadvantages of Sequential Circuits
1.Complexity: Sequential circuits are typically more complex
than combinational circuits and require more components to
implement.
2.Timing constraints: The design of sequential circuits can
be challenging due to the need to ensure that the timing of the
inputs and outputs is correct.
3.Testing and debugging: Testing and debugging sequential
circuits can be more difficult compared to combinational
circuits due to their complex structure and state-dependent
outputs.
Applications :
Sequential circuits find application in virtually almost every digital
system today because of their capacity to handle state
information. Some common applications include:
•Counters: Appearing in commonly in digital clocks, frequency
counters, and event counters.
•Registers: Found in microprocessors and digital systems as a
storage medium, a transfer medium and a medium for
manipulating data.
•Memory Elements: Used in RAM and other storage devices to
keep data in a temporary hold.
•State Machines: Made use in control systems , communication
processes, and different digital devices for state control.
Clock Signal
Clock signal is a periodic signal and its ON time and OFF time
need not be the same. We can represent the clock signal as
a square wave, when both its ON time and OFF time are same.
This clock signal is shown in the following figure.
We can represent the clock signal as train of pulses,
when ON time and OFF time are not same. This clock
signal is shown in the following figure.
Types of Triggering:

Following are the two possible types of triggering that are used in
sequential circuits.
•Level Triggering
•Edge Triggering
Level Triggering:
There are two levels, namely logic High and logic Low in clock
signal. Following are the two types of level triggering.
•Positive Level Triggering
•Negative Level Triggering

• If the sequential circuit is operated with the clock signal when

it is in Logic High, then that type of triggering is known
as Positive level triggering. It is highlighted in below figure.
• If the sequential circuit is operated with the clock signal
when it is in Logic High, then that type of triggering is
known as Positive level triggering. It is highlighted in
below figure.
If the sequential circuit is operated with the clock signal when it
is in Logic Low, then that type of triggering is known
as Negative level triggering. It is highlighted in the following
figure.
Edge Triggering:
There are two types of transitions that occur in clock signal. That
means, the clock signal transitions either from Logic Low to Logic
High or Logic High to Logic Low.

Following are the two types of edge triggering based on the

transitions of clock signal.
•Positive Edge Triggering
•Negative Edge Triggering
Positive Edge Triggering
If the sequential circuit is operated with the clock
signal that is transitioning from Logic Low to Logic
High, then that type of triggering is known
as Positive Edge Triggering. It is also called as
rising edge triggering. It is shown in the following
figure.
Negative Edge Triggering:
If the sequential circuit is operated with the clock signal that is
transitioning from Logic High to Logic Low, then that type of
triggering is known as Negative Edge Triggering.
It is also called as falling edge triggering. It is shown in the
following figure.
Memory Elements:
• In digital electronics, memory elements (also known as storage
elements) are devices or circuits used to store data in a digital
system.
• These elements allow data to be retained even after the controlling
signals or input are removed.
• Memory elements form the foundation for building more complex
digital systems like registers, memory units, and processors.
• Memory elements can store one or more bits of information and
typically operate in two primary states: Set (1) and Reset (0).
• They are crucial for enabling sequential circuits to remember
previous inputs and decisions, making them integral to digital
computers and other electronic systems.
Types of Memory Elements:
1. Latch
2. Flip-Flop
3. Registers
 LATCH:
A latch is a basic memory element that can store one bit (0 or 1).
•It works based on the input signal levels (high or low voltage).
•Latches work continuously as long as the input is active (level-sensitive).
•Flip-Flops change state only when a clock signal is applied (edge-
triggered).
•A flip-flop is basically a latch that works with a clock pulse.
•LATCH have two stable states (ON or OFF).
• LATCH are used in asynchronous circuits, meaning they do not rely on a
clock signal.
•Instead, they change states depending on the input voltage.
•Latches store data but do not need a clock.
•Flip-flops use a clock signal to control when data is stored.
•Flip-flops without a clock pulse are called latches.
Types of Latches in Digital Electronics
In digital electronics different types of latches are:
•SR Latches
•Gated SR Latches
•D Latches
•Gated D Latches
•JK Latches
•T Laches
SR Latch
• S-R latches i.e., Set-Reset latches are the simplest form of
latches and are implemented using two inputs: S (Set) and R
(Reset).
• The S input sets the output to 1(ON,) while the R input resets
the output to 0(OFF).
• When both S and R inputs are at 1, the latch is said to be in an
“undefined” state. They are also known as preset and clear
states.
• The SR latch forms the basic building blocks of all other types of
flip-flops.
Truth Table of SR Latch
The below table represents the truth table of SR latch.
Logic Diagram of SR Latch

SR Latch is a logic circuit with:

•2 cross-coupled NOR gate or 2 cross-coupled NAND gate.

•2 input S for SET and R for RESET

•2 output Q, Q’.

The below logic diagram represents the SR latch using NAND gate.

• Q (Main Output) → Holds the stored value.

•Q’ (Complement Output) → Always the opposite of Q.
The below logic diagram represents SR latch using NOR Gate.
Different Cases of SR Latch

The different cases of SR latch are discussed below.

Case 1: S’ = R’ = 1 (S = R = 0) REMAINES UNCHAGED
Gated SR Latch
A Gated SR latch is a SR latch with enable input which works when enable
is 1 and retain the previous state when enable is 0.

Truth Table of Gated SR Latch

The below table represents the truth table of Gated SR latch.
D Latch
• D latches are also known as transparent latches and are
implemented using two inputs: D (Data) and a clock signal.
• The output of the latch follows the input at the D terminal as
long as the clock signal is high.
• When the clock signal goes low, the output of the latch is
stored and held until the next rising edge of the clock.

Truth Table of D Latch

The below table represents the truth table of D latch.
Logic Diagram of D Latch

The below logic diagram represents the D latch.

Gated D Latch
D latch is similar to SR latch with some modifications made.
Here, the inputs are complements of each other. The D latch
stands for “data latch” as this latch stores single bit
temporarily.

Truth Table of Gated D Latch

The below table represents the truth table of Gated D latch.

Logic Diagram of Gated D Latch

The below logic diagram represents the gated D

latch.
JK Latch
JK latch has two inputs J and K. The output gets toggled (Toggling means switching
the output between two states (0 and 1) every time a specific event occurs, such as a clock
pulse) when the J and K inputs are high. JK latch is just like SR latch, but it
eliminates the undefined state of SR latch.

Truth Table of JK Latch

The below table represents the truth table of JK latch.

Logic Diagram of JK Latch

The below logic diagram represents the JK latch.

T Latch
When the JK inputs of JK latch are shorted we get the T latch. In T latch the outputs
are toggled when the inputs are high.

Logic Diagram of T Latch

The below logic diagram represents the T latch.

Advantages of Latches
Some of the advantages of latches are listed below.
1.Easy to Implement: Latches are simple digital circuits that can be easily implemented using basic
digital logic gates.

2.Low Power Consumption: Latches consume less power compared to other sequential circuits such
as flip-flops.

3.High Speed: Latches can operate at high speeds, making them suitable for use in high-speed digital
systems.

4.Low Cost: Latches are inexpensive to manufacture and can be used in low-cost digital systems.

5.Versatility: Latches can be used for various applications, such as data storage, control circuits, and
flip-flop circuits.

Disadvantages of Latches
Some of the disadvantages of latches are listed below.
6.No Clock: Latches do not have a clock signal to synchronize their operations, making their behavior
unpredictable.

2.Unstable State: Latches can sometimes enter into an unstable state when both inputs are at 1. This
can result in unexpected behavior in the digital system.
Flip-Flop:
• The flip-flop is a circuit that maintains a state until directed by input to
change the state.
• A basic flip-flop can be constructed using four-NAND or four-NOR gates.
Flip-flop is popularly known as the basic digital memory circuit.
• It has its two states as logic 1(High) and logic 0(low) states.
• A flip flop is a sequential circuit which consist of single binary state of
information or data.
• The digital circuit is a flip flop which has two outputs and are of
opposite states. It is also known as a Bistable Multivibrator.
Types of Flip-Flops
Given Below are the Types of Flip-Flop
•SR Flip Flop
•JK Flip Flop
•D Flip Flop
•T Flip Flop
Logic diagrams and truth tables of the different
types of flip-flops are as follows:
S-R Flip Flop
• In the flip flop, with the help of preset and clear when the power is switched
ON, the states of the circuit keeps on changing, that is it is uncertain.
• It may come to set(Q=1) or reset(Q’=0) state. In many applications, it is
desired to initially set or reset the flip flop that is the initial state of the flip
flop that needs to be assigned. This thing is accomplished by the preset(PR)
and the clear(CLR).

Block Diagram of S-R Flip Flop

Given Below is the Block Diagram of S-R Flip Flop

 Circuit Diagram and Truth Table of S-R Flip Flop
Given Below is the Diagram of S-R Flip Flop with its Truth Table
Operations of S-R Flip Flop
Given Below is the Operations of S-R Flip Flop
•Case 1(PR=CLR=1): The asynchronous inputs are inactive and
the flip flop responds freely to the S,R and the CLK inputs in the
normal way.
•Case 2(PR=0 and CLR=1):This is used when the Q is set to 1.
•Case 3(PR=1 and CLR=0):This is used when the Q’ is set to 1.
•Case 4(PR=CLR=0): This is an invalid state.
Characteristics Equation for SR Flip Flop
QN+1 = QNR’ + SR’
 J-K Flip Flop
In JK flip flops, The basic structure of the flip flop which consists of Clock (CLK), Clear
(CLR), Preset (PR).
Block Diagram of J-K Flip Flop

Given Below is Block Diagram of J-K Flip Flop

Circuit Diagram and Truth Table of J-K Flip Flop :

Given Below is the Diagram of J-K Flip Flop with its Truth Table
Operations of J-K Flip Flop
Given Below is the Operations of J-K Flip Flop
•Case 1 (PR=CLR=0 ):This condition is in its invalid state.
•Case 2 (PR=0 and CLR=1):The PR is activated which means the
output in the Q is set to 1. Therefore, the flip flop is in the set state.
•Case 3 (PR=1 and CLR=0):The CLR is activated which means
the output in the Q’ is set to 1. Therefore, the flip flop is in the reset
state.
•Case 4 (PR=CLR=1):In this condition the flip flop works in its
normal way whereas the PR and CLR gets deactivated.
Race Around Condition in J-K Flip Flop
When the J and K both are set to 1, the input remains high for a
longer duration of time, then the output keeps on toggling. Toggle
means that switching in the output instantly i.e. Q=0, Q’=1 will
immediately change to Q=1 and Q’=0 and this continuation keeps
on changing. This change in output leads to race around condition.
D Flip Flop
The D Flip Flop Consists a single data input(D), a clock input(CLK),and
two outputs: Q and Q’ (the complement of Q).

Block Diagram of D Flip Flop

Given Below is the Block Diagram of D Flip Flop
Circuit Diagram and Truth Table of D Flip Flop
Given Below is the Diagram of D Flip Flop with its Truth
Table
Operation of the D Flip-Flop
Given Below is the operation of D Flip-Flip
•Case 1 (PR=CLR=0):This conditions is represents as invalid
state where both PR(present) and CLR(clear) inputs are
inactive.
•Case 2 (PR=0 and CLR=1):This state is set state in which
PR is inactive (0) and CLR is active(1) and the output Q is set
to 1.
•Case 3 (PR=1 and CLR=0):This state is reset state in which
PR is active (1) and CLR is inactive (0) and the complementary
output Q’ is set to 1.
•Case 4 (PR=CLR=1):In This state the flip flop behaves as
normal, both PR and CLR inputs are active(1).
Characteristics Equation for D Flip Flop
QN+1 = D
T Flip Flop
The T Flip Flop consists of data input (T), a clock input (CLK),
and two outputs: Q and Q’ (the complement of Q).

Block Diagram of T Flip Flop

Given Below is the Block Diagram of T Flip Flop
Circuit Diagram and Truth Table of T Flip Flop
Given Below is the Circuit Diagram and Truth Table of T Flip Flop
Operation of the T Flip-Flop
Given Below is the Operation of T Flip-Flop
•Case 1 (T=0):In this condition the flip-flop remains in its
current state regardless of clock input,Also the Output Q will
remain unchanged unit the value of T will not change.
•Case 2 (T=1):In this condition the flip flop will change when T
input is 1,At each rising or falling edge of the clock signal the
output Q will be in complementary state.
Characteristics Equation for T Flip Flop
QN+1 = Q’NT + QNT’ = QN XOR T