8085

INTERRUPTS

1
 INTERRUPTS
 When a microprocessor is interrupted, it stops
executing its current program and calls a special
routine which “services” the interrupt

 The event that causes the interruption is called

Interrupt

 The special routine executed to service the

interrupt is called ISR - Interrupt Service
Routine/Procedure

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 INTERRUPT CLASSIFICATION
 Hardware Interrupt An interrupt caused by an “External signal ”
 Software Interrupt An interrupt caused by “Special Instruction”

 Maskable Interrupts Can be delayed or Rejected

 Non-Maskable Interrupts Can not be delayed or Rejected
(Service must)
 Vectored Where the subroutine starts is referred to as
Vector Location
 Non-vectored  The address of the service routine needs to
be supplied externally by the device
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 8085 INTERRUPTS

TRAP
RST7.5

RST6.5

RST 5.5 8085

INTR

INTA

The ‘EI’ instruction is a one byte instruction and is used

to Enable the non-maskable interrupts.
The ‘DI’ instruction is a one byte instruction and is used
to Disable the non-maskable interrupts. 4
Interrupt Name Maskable Vectored
INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes

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INTERRUPT VECTORS & THE VECTOR
TABLE

 An interrupt vector is a pointer to where the

ISR is stored in memory.
 All interrupts (vectored or otherwise) are

mapped onto a memory area called the

Interrupt Vector Table (IVT).
 The IVT is usually located in (0000H - 00FFH).

Vector Address = Interrupt number * 8

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 Vector
Interrupt Name Calculation
Address
INTR -- --
TRAP ( RST 4.5) 4.5x8=36 0024H
RST 5.5 5.5x8=44 002CH
RST 6.5 6.5x8=52 0034H
RST 7.5 7.5x8=60 003CH

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 8085 INTERRUPTS SUMMARY
Interrup Triggerin Priorit Maskabl Masking Vector
t Name g Method y e Method Address

TRAP Edge & 1st

Level Highes No None 0024H
RST 4.5 Sensitive t
Edge DI / EI
RST 7.5 2nd Yes 003CH
Sensitive SIM

Level DI / EI 0034H
RST 6.5 3rd Yes
Sensitive SIM

Level DI / EI 002CH
RST 5.5 4th Yes
Sensitive SIM

Pin
Level 5th
INTR Yes ( INTR & --
Sensitive Lowest
INTA)
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 SOFTWARE INTERRUPT
 The 8085 recognizes 8 RESTART instructions:
RST n ( RST0 - RST7)
 Each of these would send the execution to a
redetermined hard-wired memory location:

Restart Vector
Instruction Address
RST 0 CALL 0000H
RST 1 CALL 0008H
RST 2 CALL 0010H
RST 3 CALL 0018H
RST 4 CALL 0020H
RST 5 CALL 0028H
RST 6 CALL 0030H
RST 7 CALL 0038H
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THE 8085 MASKABLE/VECTORED
INTERRUPT PROCESS
1. The interrupt process should be enabled
using the EI instruction.
2. The 8085 checks for an interrupt during
the execution of every instruction.
3. If there is an interrupt, and if the interrupt
is enabled using the interrupt mask, the
microprocessor will complete the executing
instruction, and reset the interrupt flip flop.
4. The microprocessor then executes a call
instruction that sends the execution to the
appropriate location in the interrupt vector
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table.
THE 8085 MASKABLE/VECTORED
INTERRUPT PROCESS
5. When the microprocessor executes the
call instruction, it saves the address of the
next instruction on the stack.
6. The microprocessor jumps to the specific
service routine.
7. The service routine must include the
instruction EI to re-enable the interrupt
process.
8. At the end of the service routine, the RET
instruction returns the execution to where
the program was interrupted. 11
 SIM – SERIAL INTERRUPT MASK
7 6 5 4 3 2 1 0

M5.5
M7.5
M6.5
MSE
SDO

R7.5
SDE
XXX
}
RST5.5 Mask
Serial Data Out 0 - Available
RST6.5 Mask
Either 0 or 1 1 - Masked
RST7.5 Mask

Enable Serial Data Mask Set Enable

0 - Disable 0 - Ignore bits 0-2
1 - Enable 1 - Set the masks according
to bits 0-2

Not Used Force RST7.5 Flip Flop to reset

SIM VALUE MUST BE LOADED IN ACCUMULATOR 12

 Example
MSE Mask Set Enable
RST 6.5 Mask
RST 5.5 & 7.2 Unmask
RST FF Don’t Reset
Serial Data Igonered

M7.5
M6.5
M5.5
SDO

MSE
R7.5
SDE
XXX
0 0 0 0 1 0 1 0

Contents of accumulator are: 0AH

EI ; Enable interrupts including INTR

MVI A, 0A ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
SIM ; Apply the settings RST masks

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 Example
MSE Mask Set Disable
RST FF Reset
Serial Data Enable
Serial Data output is 0

M7.5
M6.5
M5.5
SDO

MSE
R7.5
SDE
XXX
0 1 0 1 0 1 0 0

Contents of accumulator are: 54H

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 RIM – READ INTERRUPT MASK

7 6 5 4 3 2 1 0

M5.5
M7.5
M6.5
P6.5
P7.5

P5.5
SDI

IE
}
RST5.5 Mask
Serial Data In 0 - Available
RST6.5 Mask
1 - Masked
RST7.5 Mask
RST5.5 Interrupt Pending
RST6.5 Interrupt Pending
RST7.5 Interrupt Pending Interrupt Enable
Value of the Interrupt Enable
Flip Flop

Set – 1
Reset - 0
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COPIES THE STATUS OF THE INTERRUPTS INTO THE
ACCUMULATOR
 Example
Interrupt Enable
RST 5.5 & 6.5 Masked
RST 7.5 Pending
Serial Input Data is 0

M7.5
M6.5
M5.5
P5.5
P7.5
SID

P6.5

IE
0 1 0 0 1 0 1 1

Contents of accumulator are: 4BH

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