|| Jai Sri Gurudev ||

Sri Adichunchanagiri Shikshana Trust (R)

SJB Institute of Technology

Department of Electronics & Communication Engineering

Advanced VLSI – 21EC71

Module-1
Introduction to ASICs
By
Mrs. S Nithya
Assistant Professor
Dept of ECE, SJBIT
 Module-1

Introduction to ASICs: Full custom, Semi-custom and Programmable ASICs,

ASIC Design flow, ASIC cell libraries. CMOS Logic: Data path Logic Cells:
Data Path Elements, Adders: Carry skip, Carry bypass, Carry save, Carry
select, Conditional sum, Multiplier (Booth encoding), Data path Operators, I/O
cells, Cell Compilers. Text Book 1

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 Introduction

• An ASIC (“a-sick”) is an application-specific integrated circuit

Figure 1.1(a) shows an IC package (this is a pin-grid array, or PGA,
shown upside down). People often call the package a chip, but, as
you can see in Figure 1.1(b), the silicon chip itself (more properly
called a die ) is mounted in the cavity under the sealed lid.
A PGA package is usually made from a ceramic material, but plastic
packages are also common.

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• The semiconductor industry has evolved from the first ICs of the early 1970s
and matured rapidly since then.
History of integration:
 small-scale integration (SSI, ~10 gates per chip, 60’s),
 medium scale integration (MSI, ~100–1000 gates per chip, 70’s),
 large-scale integration (LSI, ~1000–10,000 gates per chip, 80’s) ex: MP
 very large-scale integration (VLSI, ~10,000–100,000 gates per chip,
90’s), ex:64 bit MP, cache memory, floating pt arithmetic unit.
 ultra large scale integration (ULSI, ~1M–10M gates per chip)

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• bipolar technology and transistor–transistor logic (TTL) preceded
metal-oxide-silicon (MOS) technology because it was difficult to
make metal-gate n-channel MOS (nMOS or NMOS - 70’s).
• the introduction of complementary MOS (CMOS, never cMOS)
greatly reduced power The feature size is the smallest shape you can
make on a chip and is measured in l or lambda Origin of ASICs:
• the standard parts, initially used to design microelectronic systems,
were gradually replaced with a combination of glue logic, custom ICs,
dynamic random access memory (DRAM) and static RAM (SRAM)
• Application-specific standard products (ASSPs)
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 Types of ASIC
• IC are made on a thin circular silicon wafer. Transistor and wires are
made from many layers build on top of one another.
1. Full custom IC
2. Semi custom IC
-Standard Cell based ASIC
- Gate Array Based ASIC
-Channeled Gate Array
- Channelless Gate Array
-Structured Gate Array

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 1. Full custom IC
• A full-custom IC includes some (possibly all) logic cells that are customized
and all mask layers that are customized.
• Ex. Microprocessor, which includes a square of an micron MP chip, analog
circuit, optimized memory cells, mechanical structure of IC.
• It is Most expensive to design and manufacture. Manufacturing lead time
may take 8 weeks.
• It is suggested for specific applications.
• In a full-custom ASIC an engineer designs some or all of the logic cells,
circuits, or layout specifically for one ASIC. This approach is useful only if
there is no suitable existing library available that can be used for entire
design.
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 Cont..
• Because existing cell library are not fast enough or logic cells are small
enough or consumes too much of power then this approach is advisable.
• This full custom design are used for specialized circuits ie custom design.
• Bipolar technologies more widely used for full custom analog design because
of improved precision.
• Use of CMOS technology for analog function is increasing. Because
1. widely available
2. Increased level of integration – Mixing analog & digital function on same IC.

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 2. Semi Custom Design

• In semicustom ASICs, all of the logic cells are predesigned and some
(possibly all) of the mask layers are customized. Using predesigned cells
from a cell library makes our lives as designers much, much easier.
Semi custom IC types
-Standard Cell based ASIC
- Gate Array Based ASIC
-Channeled Gate Array
- Channelless Gate Array
-Structured Gate Array

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 Standard-Cell Based ASICs

• A cell-based ASIC (cell-based IC, or CBIC a common term in Japan,

pronounced sea-bick) uses predesigned logic cells (AND gates, OR gates,
multiplexers, and flip-flops, for example) known as standard cells.
• The standard-cell areas (also called flexible blocks) in a CBIC are built of
rows of standard cells like a wall built of bricks.
• The standard-cell areas may be used in combination with larger
predesigned cells, maybe microcontrollers or even microprocessors,
known as megacells.
• Megacells are also called megafunctions, full-custom blocks, system-level
macros (SLMs), fixed blocks, cores, or Functional Standard Blocks (FSBs).

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• The ASIC designer defines only the placement of the standard cells and the
interconnect in a CBIC.
• standard cells can be placed anywhere on the silicon; this means that all the
mask layers of a CBIC are customized and are unique to a particular
customer.
• The advantage of CBICs is that designers save time, money, and reduce
risk by using a predesigned, pretested, and precharacterized standard-cell
library.
• In addition each standard cell can be optimized individually.

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• The disadvantages are the time or expense of designing or buying the
standard-cell library and the time needed to fabricate all layers of the
ASIC for each new design.
A cell-based ASIC (CBIC) die with a
single standard-cell area (a flexible
block) together with four fixed blocks.
The flexible block contains rows of
standard cells. This is what you might
see through a low-powered microscope
looking down on the die of Figure 1.1(b).
The small squares around the edge of the
die are bonding pads that are connected
to the pins of the ASIC package. Dept. of ECE, SJBIT 12
 The important features of this type of ASIC are as follows:
 All mask layers are customized transistors and interconnect.
 Custom blocks can be embedded.
 Manufacturing lead time is about eight weeks.

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• Each standard cell in the library is constructed
using full-custom design methods, but you can
use these predesigned and precharacterized
circuits.
• This design style gives you the same
performance and flexibility advantages of a
full-custom ASIC but reduces design time and
reduces risk.
• Standard cells are designed to fit together like
bricks in a wall.
• Figure 1.3 shows an example of a simple
standard cell Power and ground buses (VDD
and GND or VSS) run horizontally on metal
lines inside the cells.

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• FIGURE 1.4 Routing the CBIC (cell-
based IC) shown in Figure 1.2. The use
of regularly shaped standard cells, such
as the one in Figure 1.3, from a library
allows ASICs like this to be designed
automatically.
• This ASIC uses two separate layers of
metal interconnect (metal1 and metal2)
running at right angles
• to each other (like traces on a printed-
circuit board). Interconnections between
• logic cells uses spaces (called channels)
between the rows of cells.
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 Gate-Array Based ASICs
• In a gate array (sometimes abbreviated to GA) or gate-array based ASIC the transistors
are predefined on the silicon wafer. The predefined pattern of transistors on a gate array
is the base array, and the smallest element that is replicated to make the base array is the
base cell (sometimes called a primitive cell ).
• To differentiate this type of gate array from other types of gate array, it is often called a
masked gate array ( MGA ).
• The designer chooses from a gate-array library of predesigned and precharacterized logic
cells. The logic cells in a gate-array library are often called macros. Macros are used to
reduce the turn around time.
• Types:
-Channeled Gate Array
- Channelless Gate Array
-Structured Gate Array
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• There are two common ways of arranging (or arraying) the
transistors on a MGA:
• in a channeled gate array we leave space between the rows of
transistors for wiring; the routing on a channelless gate array
uses rows of unused transistors.
• The channeled gate array was the first to be developed, but the
channelless gate-array architecture is now more widely used.
• A structured (or embedded) gate array can be either channeled
or channelless but it includes (or embeds) a custom block.
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1. Channeled Gate Array

The important features of this type of MGA are:

• Only the interconnect is customized.
• The interconnect uses predefined spaces between rows
of base cells.
• Manufacturing lead time is between two days and two
weeks.
 A channeled gate array is similar to a CBIC both use
rows of cells separated by channels used for
interconnect. One difference is that the space for
interconnect between rows of cells are fixed in height in
a channeled gate array, whereas the space between
rows of cells may be adjusted in a CBIC.

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2. Channelless Gate Array

The important features of this type of

MGA are as follows:
• Only some (the top few) mask layers
are customized the interconnect.
• Manufacturing lead time is between
two days and two weeks.

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• The key difference between a channelless gate array and channeled
gate array is that there are no predefined areas set aside for routing
between cells on a channelless gate array. Instead we route over the
top of the gate-array devices.
• We can do this because we customize the contact layer that defines the
connections between metal1, the first layer of metal, and the
transistors.
• When we use an area of transistors for routing in a channelless array, we
do not make any contacts to the devices lying under the transistor. we
simply leave the transistors unused.
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• The logic density the amount of logic that can be implemented
in a given silicon area is higher for channelless gate arrays than
for channeled gate arrays. This is usually attributed to the
difference in structure between the two types of array.
• In fact, the difference occurs because the contact mask is
customized in a channelless gate array, but is not usually
customized in a channeled gate array. This leads to increase the
density of gate-array cells because we can route over the top of
unused contact sites.
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 3. Structured Gate Array
• An embedded gate array or structured gate array (also known as
masterslice or master image ) combines some of the features of CBICs and
MGAs.
• One of the disadvantages of the MGA is the fixed gate-array base cell.
This makes the implementation of memory, for example, difficult and
inefficient.
• In an embedded gate array we set aside some of the IC area and dedicate
it to a specific function. This embedded area either can contain a different
base cell that is more suitable for building memory cells, or it can contain
a complete circuit block, such as a microcontroller.

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 The important features of this type of
MGA are the following:
• Only the interconnect is customized.
• Custom blocks (the same for each
design) can be embedded.
• Manufacturing lead time is between
two days and two weeks.

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• An embedded gate array gives the improved area efficiency and
increased performance of a CBIC but with the lower cost and faster
turnaround of an MGA.
• One disadvantage of an embedded gate array is that the embedded
function is fixed.
• For example, if an embedded gate array contains an area set aside for a 32
k-bit memory, but we only need a 16 k-bit memory, then we may have to
waste half of the embedded memory function.
• However, this may still be more efficient and cheaper than
implementing a 32 k-bit memory using macros on a SOG array.
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 Programmable Logic Devices
• Programmable logic devices ( PLDs ) are standard ICs that are
available in standard configurations.
• PLDs may be configured or programmed to create a part
customized to a specific application, and so they also belong to the
family of ASICs.
• PLDs use different technologies to allow programming of the
device.

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CRYPTOGRAPHY-
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MODULE-1
following important features that all PLDs have in common:
• No customized mask layers or logic cells
• Fast design turnaround
• A single large block of programmable interconnect
• A matrix of logic macrocells that usually consist of
programmable array logic followed by a flip-flop or latch

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• The simplest type of programmable IC is a read-only memory (ROM).
The most common types of ROM use a metal fuse that can be
carried permanently.
• An electrically programmable ROM , or EPROM , uses programmable
MOS transistors whose characteristics are altered by applying a
high voltage. You can erase an EPROM either by using another high
voltage (an electrically erasable PROM , or EEPROM ) or by exposing
the device to ultraviolet light ( UV-erasable PROM , or UVPROM ).

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• There is another type of ROM that can be placed on any ASIC a
mask-programmable ROM (mask-programmed ROM or masked
ROM). A masked ROM is a regular array of transistors permanently
programmed using custom mask patterns. An embedded masked
ROM is thus a large, specialized, logic cell.
• The same programmable technologies used to make ROMs can be
applied to more flexible logic structures. By using the
programmable devices in a large array of AND gates and an array of
OR gates, we create a family of flexible and programmable logic
devices called logic arrays .
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• we have a mask-programmable ROM, we could place a logic array as a cell
on a custom ASIC. This type of logic array is called a programmable logic
array (PLA).
• There is a difference between a PAL and a PLA: a PLA has a programmable
AND logic array, or AND plane , followed by a programmable OR logic array,
or OR plane ; a PAL has a programmable AND plane and, in contrast to a
PLA, a fixed OR plane.
• Depending on how the PLD is programmed, we can have an erasable PLD
(EPLD), or mask-programmed PLD. The first PALs, PLAs, and PLDs were
based on bipolar technology and used programmable fuses or links. CMOS
PLDs usually employ floating-gate transistors.
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PLA

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PAL

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 Field-Programmable Gate Arrays

• There is very little difference between an FPGA and a PLD an

FPGA is usually just larger and more complex than a PLD. In
fact, some companies that manufacture programmable ASICs call
their products FPGAs and some call them complex PLDs .
• FPGAs are the newest member of the ASIC family and are rapidly
growing in importance, replacing TTL in microelectronic systems.
Even though an FPGA is a type of gate array, we do not consider
the term gate-array based ASICs to include FPGAs.

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the essential characteristics of an FPGA:
• None of the mask layers are customized.
• A method for programming the basic logic cells and the interconnect.
• The core is a regular array of programmable basic logic cells that can
implement combinational as well as sequential logic (flip-flops).
• A matrix of programmable interconnect surrounds the basic logic cells.
• Programmable I/O cells surround the core.
• Design turnaround is a few hours.

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Dept. of ECE, SJBIT 35
Design Flow

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1. Design entry. Enter the design into an ASIC design system, either using a hardware
description language ( HDL ) or schematic entry .
2.Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis tool to produce
a netlist a description of the logic cells and their connections.
3. System partitioning. Divide a large system into ASIC-sized pieces.
4. Prelayout simulation. Check to see if the design functions correctly.
5. Floorplanning. Arrange the blocks of the netlist on the chip.
6. Placement. Decide the locations of cells in a block.
7.Routing. Make the connection between the logic cells
8.Extraction. Determine the resistance and capacitance of the interconnect.
9. Post layout simulation. Check to see the design still works with the added loads of
the interconnect.
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