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DLCA M2 GATE Activity

The document contains a series of questions and answers related to processor organization and architecture, focusing on instruction formats, opcode calculations, and memory consumption. It includes calculations for immediate operand bits, unique opcode possibilities, maximum values for immediate operands, and memory requirements for a set number of instructions. Each section is attributed to different group members, showcasing their individual problem-solving approaches.

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3 views

DLCA M2 GATE Activity

The document contains a series of questions and answers related to processor organization and architecture, focusing on instruction formats, opcode calculations, and memory consumption. It includes calculations for immediate operand bits, unique opcode possibilities, maximum values for immediate operands, and memory requirements for a set number of instructions. Each section is attributed to different group members, showcasing their individual problem-solving approaches.

Uploaded by

ujjay.18024
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 17

GATE ACTIVITY

MODULE 2

PROCESSOR
ORGANISATION &
ARCHITECTURE
Group Members

1. Zeal Gori - 21
2. Ujjay Manety - 33
3. Vansh Mojidra - 36
4. Kasak Vakharia - 60
ZEAL GORI - 21
Q) A processor has 40 distinct instructions and 24 general purpose
registers. A 32-bit instruction word has an opcode, two register
operands and an immediate operand. The number of bits available for
the immediate operand field is ____ .
GATE CSE 2016 Set
2
Determine opcode bits:
● Number of instructions = 40
● Opcode bits =[log2(40)]=6

Determine register operand bits:


● Number of registers = 24
● Register operand bits = ⌈log⁡2(24)⌉=5
Calculate bits used for opcode and register operands:
● Total bits for two register operands = 5 (reg1)+ 5(reg2) = 10
● Total bits used = 6(opcode) + 10(registers) = 16

Calculate remaining bits for immediate operand:


● Total instruction bits = 32
● Immediate operand bits = 32 − 16 = 1632 - 16 = 1632 − 16 = 16

Final answer:

The number of bits available for the immediate operand field is 16 bits.
UJJAY MANETY - 33
Q) A processor with 16 general purpose registers uses a 32-bit instruction
format. The instruction format consists of an opcode field, an addressing
mode field, two register operand fields, and a 16-bit scalar field. If 8
addressing modes are to be supported, the maximum number of unique
opcodes possible for every addressing mode is _________
GATE CSE 2024 Set
2
To determine the maximum number of unique opcodes possible for every
addressing mode, we start by analyzing the structure of the 32-bit
instruction format based on the given components:

1. Addressing Mode Field: Since there are 8 addressing modes, we


need log2​(8) = 3 bits to represent the addressing mode.
1. Register Operand Fields: The processor has 16 general-purpose
registers, which requires log⁡2(16) = 4 bits for each register operand.
Since there are two register operand fields, this contributes 4×2 = 8 bits.
2. Scalar Field: The scalar field is 16 bits long.

● Instruction size = 32 bits


● Given that no. of Registers = 16
● So no. of bits needed to specify a register in instruction = 4
● Given that no. of Addressing modes = 8
● So no. of bits needed to specify an addressing mode in instruction
=3
No. of bits available for opcode =
Instruction size - (Addressing mode field size + 2 * Register
field size + Scalar field size)

= 32 - (3 + 2*4 + 16)

= 32 - 27

=5

So maximum no. of unique opcodes possible = 2^5 = 32


VANSH MOJIDRA - 36
Q) A machine has a 32-bit architecture, with 1-word long instructions. It
has 64 registers, each of which is 32 bits long. It needs to support 45
instructions, which have an immediate operand in addition to two register
operands. Assuming that the immediate operand is an unsigned integer,
the maximum value of the immediate operand is ____________.

GATE CSE 2014 SET 1

BITS FOR OPCODES = LOG 2(45) = 6 BITS …… AS INSTRUCTIONS


=45

BITS FOR EACH REGISTERS = LOG 2(64) =6 BITS …… AS REGISTERS =


64

AS THERE ARE 2 REGISTER OPERANDS = 2 * 6 =12 BITS


BITS FOR IMMEDIATE OPERAND

= 32-( BITS FOR OPCODES + BITS FOR REGISTERS OPERANDS)

= 32 -(6+12)= 14 BITS

MAXIMUM VALUE FOR IMMEDIATE OPERAND

= 2n -1

= 214 -1

= 16383
KASAK VAKHARIA -
60
Q) Consider a processor with 64 registers and an instruction
set of size twelve. Each instruction has five distinct fields,
namely, opcode, two source register identifiers, one destination
register identifier, and twelve-bit immediate value. Each
instruction must be stored in memory in a byte-aligned
fashion. If a program has 100 instructions, the amount of
memory (in bytes) consumed by the program text is
_________.

GATE CSE 2016 Set 2


Number of registers = 64
Number of bits to address register = log2⁡(64) = 6 - bits

Number of Instructions = 12
Opcode size =log2(⁡12) = 4

Total bits per instruction = 34


Total bytes per instruction = 4.25
Due to byte alignment we cannot store 4.25 bytes, without wasting 0.75 bytes.
So, total bytes per instruction = 5
Total number of instructions = 100
Total size = Number of instructions × Size of an instruction
= 100×5
= 500 bytes

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