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VHDL_Lec6

This chapter covers combinational logic circuits, including multiplexers, demultiplexers, decoders, encoders, and code converters, along with their VHDL implementations. It explains the functionality of these circuits, emphasizing the importance of truth tables and Boolean algebra in their design. Additionally, it provides exercises for implementing various multiplexers, encoders, decoders, and arithmetic circuits in VHDL.

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4 views

VHDL_Lec6

This chapter covers combinational logic circuits, including multiplexers, demultiplexers, decoders, encoders, and code converters, along with their VHDL implementations. It explains the functionality of these circuits, emphasizing the importance of truth tables and Boolean algebra in their design. Additionally, it provides exercises for implementing various multiplexers, encoders, decoders, and arithmetic circuits in VHDL.

Uploaded by

ogunwandeemmanuel8
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Combinational Logic

The objectives of the chapter are to describe:


Combinational logic circuits
Multiplexers and demultiplexers
Decoders and encoders
Code converters
Arithmetic circuits
Comparison circuits
VHDL codes for basic combinational circuits
• Tools required to build combinational circuits: truth table design, basic
knowledge of Boolean algebra, and implementation using logic gates.
Block Diagram of a Combinational Circuit

• The outputs from a combinational logic circuit depend only on the current
inputs. In other words, a combinational circuit is a set of interconnected
gates whose output at any time is a function of the input at that time. E.g.
multiplexers, decoders, encoders, and code converters.
• On the other hand, sequential circuits are composed of combinational
circuits and memory elements with a set of m inputs and a set of n outputs.
MULTIPLEXERS
• A multiplexer (or “mux”) is a digital switch that has data inputs, M select
(control) inputs, and a single output. It routes data from one of data
inputs to its single output. The select input lines control which data input is
connected to the output.
• Thus, a multiplexer acts as a programmable digital switch.
2 : 1 Multiplexer
• 2 : 1 Multiplexer - : 1 (pronounced “ to 1”) multiplexer has two data inputs,
one select input, and a single output.
• The function of a 2 : 1 multiplexer is described by the truth table below:
VHDL Code for a 2 : 1 Multiplexer Using Select Signal Assignment

library ieee ;
use ieee.std_logic_1164.all;

entity mux2to1 is
port(
x1,x2,s : in std_logic;
f : out std_logic);
end mux2to1;
architecture circuit_behavior of mux2to1 is
begin
with s select
f <= x1 when ‘0’;
x2 when others;
end circuit_behavior;
VHDL Code for a 2 : 1 Multiplexer Using Conditional Signal Assignment

library ieee ;
use ieee.std_logic_1164.all;

entity mux2to1 is
port(
x1,x2,s : in std_logic;
f : out std_logic);
end mux2to1;
architecture circuit_behavior of mux2to1 is
begin
f <= x1 when s=‘0’ else x2;
end circuit_behavior;
VHDL Code for a 2 : 1 Multiplexer Using an If–Else–Then Statement
library ieee ;
use ieee.std_logic_1164.all;

entity mux2to1 is
port(
x1,x2,s : in std_logic;
f : out std_logic);
end mux2to1;
architecture circuit_behavior of mux2to1 is
begin
process (x1,x2,s)
begin
if s=‘0’ then;
f <= x1;
else
f <= x2;
end if;
end process;
end circuit_behavior;
VHDL Code for a 2 : 1 Multiplexer Using a Case Statement
library ieee ;
use ieee.std_logic_1164.all;

entity mux2to1 is
port(
x1,x2,s : in std_logic;
f : out std_logic);
end mux2to1;
architecture circuit_behavior of mux2to1 is
begin
process (x1,x2,s)
begin
case s is;
when ‘0’ => f <= x1;
when others => f <= x2;
end case;
end process;
end circuit_behavior;
4 : 1 Multiplexer
• A 4 : 1 multiplexer has four data inputs, two select inputs, and a single
output.
• The function of the 4 : 1 multiplexer is described using a truth table below:
VHDL Code for a 4 : 1 Multiplexer Using a Select Signal Assignment
use ieee.std_logic_1164.all;

entity mux4to1 is
port(
x1,x2,x3,x4 : in std_logic;
s : in std_logic_vector(1 downto 0);
f : out std_logic);
end mux4to1;
architecture circuit_behavior of mux4to1 is
begin
with s select
f <= x1 when “00”;
x2 when “01”;
x3 when “10”;
x4 when others;
4 : 1 multiplexer can be implemented using three 2 : 1
multiplexers
A larger multiplexer could be designed using smaller multiplexers as modules.
The data inputs of the smaller multiplexers are funneled down to a single
output.

Implementation of a 4 : 1 Multiplexer Using Three 2 : 1 Multiplexers


DEMULTIPLEXERS
• This circuit takes a single data input and one or more address inputs and
selects which of multiple outputs will receive the input signal. The same
circuit can also be used as a decoder by using the address inputs as a binary
number and producing an output signal on the single output that matches
the binary address input.

XOR Logic Function Implementation with a 2 : 1 Multiplexer


DECODERS
• A decoder is a multiple-input, multiple-output logic circuit that converts
coded inputs into coded outputs, where the input and output codes are
different. The input code generally has fewer bits than the output code, and
there is one-to-one mapping from input code words into output code words.
2 : 4 Decoder
ENCODERS
• An encoder performs the function opposite to that of a decoder. It encodes
the given information into a more compact form. The most commonly used
encoders are binary encoders and priority encoders.
Binary Encoder
• Exactly one of the input signals should have a value of 1, and the outputs present the
binary number that identifies which input is equal to 1.
• A binary encoder converts only one input at a time into a binary code.
• In the 4 : 2 binary encoder, which has four inputs and two outputs shown below only one
input is set at any time.
Priority Encoder
• A priority encoder is an encoder where more than one input can be activated
simultaneously. Each input is assigned a priority order. When the input with
the highest priority is asserted, the remaining inputs are ignored.
CODE CONVERTERS
• There are many other possible types of code converters apart from decoder
and encoder known as BCD-to-seven-segment code converter, BCD-to-Gray
code converter, BCD-to-excess-3 code converters, and so on.
BCD-to-Seven-Segment Code Converter
• A BCD-to-seven-segment code converter converts one binary-coded decimal
(BCD) digit into information suitable for driving a digit-oriented display such
as a seven-segment display. i.e. it converts the BCD digit into seven signals
that are used to drive the segments in the display.
• The circuit of the BCD-to-seven-segment code converter has four binary
inputs (x1, x2, x3, and x4), representing the BCD number, and seven binary
outputs (a, b, c, d, e, f, and g) representing the LED segments.
• Each segment is a small LED, which glows when driven by an electrical signal.
• The BCD-to-segment code conversion truth table and a seven-segment LED
display are shown below.
VHDL Code Implementation of the BCD-to-Seven-Segment Code Converter
BCD-to-Gray Code Converter
• Gray code is an encoding scheme in which two consecutive binary numbers
change by only 1 bit. Each number in a Gray code sequence differs from its
predecessor by exactly 1 bit.
• The circuit has four inputs (x1, x2, x3, and x4) representing the BCD number,
and four outputs (y1, y2, y3, and y4) representing the 4-bit Gray code number.
BCD-to-Excess-3 Code Converter
• The BCD-to-excess-3 code converter converts a given BCD number into a
number that can be obtained by adding the number three (0011) to it.
Excess-3 code was used in older computer systems.
• An important characteristic of excess-3 code is its self-complementing
property, similar to that of the 1’s-complement method.
ARITHMETIC CIRCUITS: Adder
• Addition is the most commonly performed arithmetic operation in digital
systems.
• An adder is a digital circuit that adds two N-bit numbers and generates an N-
bit number.
• An adder can perform subtraction as the addition of the minuend and the
complemented subtrahend.
• Direct implementation of an N-bit adder would be very complex and not
scalable, therefore, a simpler approach would be to build an N-bit adder
from smaller module circuits, which can be duplicated and expanded as the
size of the adder increases.
Half-Adder
• A 1-bit half-adder adds two 1-bit operands, x and y, and produces a 2-bit
result.
• The low-order bit of the sum is referred to as s (sum) and the high-order bit
as cout (carryout).
Exercise
• Write VHDL code to implement a 4 : 1 multiplexer.
• Write VHDL code to implement a 4 : 1 multiplexer using a when–else
statement.
• Write VHDL code to implement a 4 : 1 multiplexer using an if–then–else
statement.
• Write VHDL code to implement a 4 : 1 multiplexer using a case statement.
• Write VHDL code to implement a 16 : 1 multiplexer using 4 : 1 multiplexers.
• Write VHDL code to implement an 8 : 3 priority encoder.
• Write VHDL code to implement a 3 : 8 binary decoder.
• Write VHDL code to implement a 3-bit priority encoder.
• Write VHDL code to implement a BCD-to-seven-segment encoder using a
select signal assignment.
• Design a 4-bit ripple-carry adder.

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