University Of Diyala

College Of Engineering
Computer Engineering Department

COMPUTER ARCHITECTURE I

LECTURE 2
REGISTER TRANSFER AND MICRO-
OPERATIONS
Lecturer. Ahmed Salah Hameed
Second stage
2019-2020

1
 CONTE
NTS
• Register Transfer Language

• Register Transfer

• Bus and Memory Transfers

• Arithmetic Micro-operations

• Logic Micro-operations

• Shift Micro-operations

• Arithmetic Logic Shift Unit

2
4-1 REGISTER TRANSFER LANGUAGE
(RTL)

Digital System: An interconnection of

hardware modules that do a certain task on
the information.
Registers + Operations performed on the
data stored in them = Digital Module
Modules are interconnected with common
data and control paths to form a digital
computer system

3
4-1 REGISTER TRANSFER LANGUAGE CONT.

Microoperations: operations executed on

data stored in one or more registers.
For any function of the computer, a
sequence of Microoperations is used to
describe it
The result of the operation may be:
• replace the previous binary information of a register or
• transferred to another register

Shift Right Operation

101101110011 010110111001

4
4-1 REGISTER TRANSFER LANGUAGE CONT.

The internal hardware organization of a digital computer is

defined by specifying:
• The set of registers it contains and their function
• The sequence of microoperations performed on the binary
information stored in the registers
• The control that initiates the sequence of microoperations

Registers + Microoperations Hardware +

Control Functions = Digital Computer

5
4-1 REGISTER TRANSFER LANGUAGE CONT.

a symbolic notation
Register Transfer Language (RTL) :
to describe the Microoperations transfers
among registers
Next steps:
• Define symbols for various types of Microoperations,
• Describe the hardware that implements these
Microoperations

6
4-2 REGISTER TRANSFER
(OUR FIRST MICRO-OPERATION)

Computer registers are designated by capital letters

(sometimes followed by numerals) to denote the function of
the register
• R1: processor register
• MAR: Memory Address Register (holds an address for a
memory unit)
• PC: Program Counter
• IR: Instruction Register
• SR: Status Register

7
4-2 REGISTER TRANSFER CONT.

The individual flip-flops in an n-bit register are numbered in

sequence from 0 to n-1 (from the right position toward the
left position)

R1 7 6 5 4 3 2 1 0

Register R1 Showing individual bits

A block diagram of a register

8
4-2 REGISTER TRANSFER CONT.

Other ways of drawing the block diagram of a register:

15 0
PC

Numbering of bits

15 87 0
Upper byte PC(H) PC(L) Lower byte
Partitioned into two parts

9
4-2 REGISTER TRANSFER CONT.

Information transfer from one register to another is described by a

replacement operator: R2 ← R1
This statement denotes a transfer of the content of register R1
into register R2
The transfer happens in one clock cycle
The content of the R1 (source) does not change
The content of the R2 (destination) will be lost and replaced by the
new data transferred from R1
We are assuming that the circuits are available from the outputs
of the source register to the inputs of the destination register, and
that the destination register has a parallel load capability

10
4-2 REGISTER TRANSFER CONT.

Conditional transfer occurs only under a control condition

Representation of a (conditional) transfer

P: R2 ← R1
A binary condition (P equals to 0 or 1) determines when the
transfer occurs
The content of R1 is transferred into R2 only if P is 1

11
 4-2 REGISTER TRANSFER CONT.

Hardware implementation of a controlled transfer:

P: R2 ← R1
Block diagram: Control P Load
R2 Clock
Circuit

R1

t t+1

Timing diagram
Clock
Synchronized
Load
with the clock
Transfer occurs here

12
 4-2 REGISTER TRANSFER CONT.

Basic Symbols for Register Transfers

Symbol Description Examples
Letters & Denotes a register MAR, R2
numerals
Parenthesis ( ) Denotes a part of a R2(0-7), R2(L)
register
Arrow ← Denotes transfer of R2 ← R1
information
Comma , Separates two R2 ← R1, R1 ← R2
microoperations

13
4-3 BUS AND MEMORY TRANSFERS

Paths must be provided to transfer information

from one register to another
A Common Bus System is a scheme for
transferring information between registers in a
multiple-register configuration
A bus: set of common lines, one for each bit of
a register, through which binary information is
transferred one at a time
Control signals determine which register is
selected by the bus during each particular
register transfer

14
4-3 BUS AND MEMORY TRANSFERS
Register A Register B Register C Register D

Bus lines

Register D Register C Register B Register A

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

D3 D2 D1 D0 C3 C2 C1 C0 B3 B 2 B 1 B 0 A3 A 2 A 1 A 0

D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0

3 2 1 0 3 2 1 0 3 2 1 0
3 2 1 0 S0
S0 S0 S0
MUX3 MUX2 MUX1 MUX0 S1
S1 S1 S1

4-Line Common Bus

15
4-3 BUS AND MEMORY TRANSFERS

The transfer of information from a bus into

one of many destination registers is done:
By connecting the bus lines to the inputs of all
destination registers and then:
 activating the load control of the particular destination
register selected
We write: R2 ← C to symbolize that the
content of register C is loaded into the
register R2 using the common system bus
 It is equivalent to: BUS ←C, (select C)
R2 ←BUS (Load R2)

16
4-3 BUS AND MEMORY TRANSFERS:
THREE-STATE BUS BUFFERS

A bus system can be constructed with three-state buffer

gates instead of multiplexers
A three-state buffer is a digital circuit that exhibits three
states: logic-0, logic-1, and high-impedance (Hi-Z)

Control input C

Normal input A Output B

Three-State Buffer

17
4-3 BUS AND MEMORY TRANSFERS:
THREE-STATE BUS BUFFERS CONT.

C=1

Buffer
A B A B

C=0

Open Circuit
A B A B

18
4-3 BUS AND MEMORY TRANSFERS:
THREE-STATE BUS BUFFERS CONT.

S1 0
Select
S0 1
Bus line for bit 0
2×4 A0
Decoder 2
Enable E
3

B0

C0

Bus line with three-state

buffer (replaces MUX0 in the
previous diagram) D0

19
4-3 BUS AND MEMORY TRANSFERS:
MEMORY TRANSFER
 Memory read : Transfer from memory
 Memory write : Transfer to memory
 Data being read or wrote is called a memory
word (called M).
 It is necessary to specify the address of M
when writing /reading memory.
 This is done by enclosing the address in
square brackets following the letter M.
 Example: M[0016] : the memory contents at
address 0x0016

20
4-3 BUS AND MEMORY TRANSFERS:
MEMORY TRANSFER CONT.

21
21
4-3 BUS AND MEMORY TRANSFERS:
MEMORY TRANSFER CONT.

Assume that the address of a memory unit is stored in a

register called the Address Register AR

Lets represent a Data Register with DR, then:

Read: DR ← M[AR]
Write: M[AR] ← DR

22
4-3 BUS AND MEMORY TRANSFERS:
MEMORY TRANSFER CONT.

AR
x0C 19
x12 x0E 34
R1 x10 45
100 x12 66
x14 0
x16 13
R1←M[AR] x18 22

RAM

R1 R1
100 66

23
SUMMARY OF REGISTER
TRANSFER MICROOPERATIONS

24
24