BECE102L – Digital Systems

Design
Module – 2 Verilog HDL

Dr. K. Chitra
Professor
School of Electronics Engineering
AB1-607A – Cabin no. 6
9500146958
 Module-2 (Verilog HDL)
Lexical Conventions, Ports and Modules,
Operators, Data flow modeling, Gate level
modeling, Behavioral modeling, Test Bench
 HDL
• Hardware Description Language (HDL) is a
computer-based language that describes the
hardware of a digital system in textual form.
• HDL describes
– hardware structures, and the behavior of logic
circuits.
– logic diagram, truth tables, Boolean expressions,
and complex abstraction of the behavior of a
digital system.
 HDLs
• Two most widely used HDLs and supported by IEEE are
– Verilog
– VHDL (VHSIC HDL – Very High Speed Integrated Circuit HDL)
• HDLs are used in major steps in the design flow of an
integrated circuit:
– Design entry
– Functional simulation or verification
– Logic synthesis
– Timing verification
– Fault simulation
 Features of Verilog
• Verilog
– Composed of text using keywords about 100
– Keywords are predefined lowercase identifiers.
Ex. module, endmodule, input, output, wire, and,
or, not
– Text between “//” and end of the line – comment
– Multiline comment appears between /* and */
– Verilog is case sensitive
 Lexical Conventions
• Logical values: 0, 1, X, Z
• Types of lexical tokens:
– Operators,
– white space,
– comment,
– Identifiers,
– number,
– string,
– Keywords (indicated in bold face)
 Types of Operators
Arithmetic Operators +, -, *, /, %
Relational Operators <, <=, >, >=
Equality Operators ==, !=, ===, !==
Logical Operators !, &&, ||
Bit-Wise Operators ~, &, |, ^, ~^
Unary Reduction &, ~&, |, ~|, ^, ~^
Shift Operators >>, <<
Conditional Operators ?:
Concatenations {}
 Operators..
{} concatenation ~ bit-wise NOT
+ - * / arithmetic & bit-wise AND
% modulus | bit-wise OR
> >= < <= relational ^ bit-wise XOR
^~ ~^ bit-wise XNOR
! logical NOT
& reduction AND
&& logical AND
| reduction OR
|| logical OR ~& reduction NAND
== logical equality ~| reduction NOR
!= logical ^ reduction XOR
inequality ~^ ^~ reduction XNOR
?: conditional << shift left
>> shift right
 Precedence of operators
[ ]bit-select or part-select >, >=, <, <= relational
( ) parentheses ==, != logical equality
!, ~ logical and bit-wise & bit-wise AND
negation ^, ^~, ~^
&, |, ~&, ~|, ^, ~^, ^~ bit-wise XOR and XNOR
reduction operators | bit-wise OR
+, - unary arithmetic && logical AND
{ }concatenation || logical OR
*, /, % arithmetic ?: conditional
+, - arithmetic
<<, >> shift
 Other lexicals..
• Comments: //, /* */
• Numbers: Decimal, hexa, octal, binary
• String: “Enclose between quotes”
• Identifiers:
– A..Z, a…z, 0..9, underscore and dollar sign
– Limited to 1024 characters long
– First character of identifier must not be a digit
– Verilog has Case sensitive characters
Keywords
 Data types
1. Value sets (Logical 0, 1, x, z)
2. Nets
3. Vectors
4. Registers
5. Integer, real and time register
6. Arrays
7. Memories
8. Parameters
9. Strings
Numeric Constants
 Data types
• Nets
– Nets are physical connections between devices.
– Nets always reflect the logic value of the driving device.
– Following types of nets are there, but wire is often used
– types of nets
• wire, tri : default
• wor, trior : wire-ORed
• wand, triand : wire-ANDed
• trireg : with capacitive storage
• tri1 : pull high
• tri0 ; pull low
• supply1 ; power
• supply0 ; ground
 Registers and parameters
• Registers & Parameters
– Implicit storage – Does not necessarily imply a
hardware register.
– Register type is denoted by reg .
A register holds its value until a new value is
assigned to it.
Registers are used extensively in behavior
modeling and in applying stimuli.
Parameters are not variables, they are constants.
 Variable Declaration
• Declaring a net
wire [<range>] <net_name> [<net_name>*];
Range is specified as [MSB:LSB]. Default is one bit wide

• Declaring a register
reg [<range>] <reg_name> [<reg_name>*];

• Declaring memory
reg [<range>] <memory_name> [<start_addr> : end_addr>];

• Examples
reg r; // 1-bit reg variable
wire w1, w2; // 2 1-bit wire variable
reg [7:0] vreg; // 8-bit register
reg [7:0] memory [0:1023]; a 1 KB memory
Integer and real register data type
• Integers are declared by the keyword integer.
The default width is 32 bits

• Real number constants and real register data

types are declared with the keyword real.
 Time register data type
• Verilog simulation is done with respect to simulation
time.
• A special time register data type is used in Verilog to
store simulation time.
• A time variable is declared with the keyword time.
 Arrays
• Arrays are allowed in Verilog for reg, integer, time, real, real
time and vector register data types.
• Multi-dimensional arrays can also be declared with any
number of dimensions.
• Arrays of nets can also be used to connect ports of
generated instances.
• Each element of the array can be used in the same fashion
as a scalar or vector net.
• Arrays are accessed by <array_name> [<subscript>]
• A vector is a single element that is n-bits wide, whereas
arrays are multiple elements that are 1-bit or n-bits wide.
 Strings
• Strings can be stored in reg.
• The width of the register variables must be large enough
to hold the string.
• Each character in the string takes up 8 bits (1 byte), if the
width of the register is greater than the size of the string,
• If the register width is smaller than the string width,
Verilog truncates the leftmost bits of the string
Data types for ports
 System tasks
• All system tasks appear in the form $<keyword>.
• Operations such as displaying on the screen,
monitoring values of nets, stopping, and finishing
are done by system tasks.
• Displaying information: $display(p1,p2,p3,..pn)
– p1, p2, p3,..., pn can be quoted strings or variables or
expressions.
– A $display without any arguments produces a newline.
String format specs
 HDL
Different levels of abstraction possible:
• Algorithmic level System

• Architectural level
Algorithm
• Register transfer level (RTL)
• Gate level Architecture

• Switch (Transistor) level Register Transfer

Level

Gate Level

Transistor Level
 Verilog
• 3 levels of abstraction in Verilog:
– Gate level
• Circuit is modeled by logic gates
• Logic gates are predefined in Verilog library
– Data flow level
• Assignment statement is used (assign)
– Behavioral / Algorithmic level
• A region of code containing sequential statements
 Gate level modeling
In gate level modeling a circuit can be defined by use of logic gates.
These gates predefined in verilog library.
The basic gates and their syntax is as follows:
not gate_name (output, input);
and gate_name(output, input);
or gate_name(output, input);
nand gate_name(output, input);
nor gate_name(output, input);
xor gate_name(output, input);
xnor gate_name(output, input);
 Verilog Primitives
• Basic logic gates only
– and
– or
– not
– buf
– xor
– nand
– nor
– xnor
– bufif1, bufif0
– notif1, notif0
 Multiple inputs
• One output and variable number of inputs

• not and buf

– variable number of outputs but only one input
 Example
module generate_sum (a, b, c);
input a, b;
output c;
xor g1(c, a, b);
endmodule
Multiplexer
Logic diagram - Multiplexer
 Data flow modeling
Continuous assignment statement is used.
Syntax :
assign(strength, strength) #(delay) net = expression;

Keyword assign is used followed by =

 assign y = ~ x ; // NOT
 assign y = a & b; // AND
 assign w = a ^ b;// Ex-OR
 assign x = a + b; // OR
 assign y = s ? b : a // 2×1 multiplexer
when s = 1 , y = b
when s = 0 , y = a
 assign eq = (a==b); // comparator
 wire #10 inv = ~in ; // inverter with delay
 wire [7:0] c = a+b ; // 8-bit adder
 Example – Data flow modeling
module practice (y, a, b); // module definition
input a, b; // by default it takes 1 bit input
output y; // one bit output
assign y = a & b;
endmodule
Data flow modeling – 4-1 MUX
Examples of continuous assign
 Delays
• Delay values control the time between the
change in a right-hand-side operand and when
the new value is assigned to the left-hand
side.
• Three ways of specifying delays in continuous
assignment statements are
– regular assignment delay, implicit continuous
assignment delay, and net declaration delay.
 Expressions, operators and operands
• Expressions are constructs that combine operators and
operands to produce a result
Operators
 Arithmetic operators
• There are two types of arithmetic operators: binary and unary.
• Binary arithmetic operators are multiply (*), divide (/), add (+),
subtract (-), power (**), and modulus (%).
• Binary operators take two operands, whereas unary takes one.
 Operators..
• If any operand bit has a value x, then the
result of the entire expression is x.
• if an operand value is not known precisely, the
result should be an unknown.
 Unary operators
• The operators + and - can also work as unary operators.
• They are used to specify the positive or negative sign of the operand.
Unary + or ? operators have higher precedence than the binary + or ?
operators.
– -4 // Negative 4
– +5 // Positive 5
• Negative numbers are represented as 2's complement internally in
Verilog.
• It is advisable to use negative numbers only of the type integer or real
in expressions.
• Designers should avoid negative numbers of the type <sss> '<base>
<nnn> in expressions because they are converted to unsigned 2's
complement numbers and hence yield unexpected results.
 Logical operators
• Logical operators are
– logical-and (&&),
– logical-or (||) and
– logical-not (!).
• Binary operators are
– Binary-and (&)
– Binary-or (|)
• Operator ! is a unary operator.
 Logical operators
• Logical operators take variables or expressions as
operands.
– Logical operators always evaluate to a 1-bit value, 0
(false), 1 (true), or x (ambiguous).
– If an operand is not equal to zero, it is equivalent to a
logical 1 (true condition).
– If it is equal to zero, it is equivalent to a logical 0 (false
condition).
– If any operand bit is x or z, it is equivalent to x
(ambiguous condition) and is normally treated by
simulators as a false condition.
Logical operators
 Relational operators
• Relational operators are
– greater-than (>), less-than (<), greater-than-or-equal-to (>=), and less-
than-or-equal-to (<=).
• The expression returns a logical value of
– 1 if the expression is true and
– 0 if the expression is false.
• If there are any unknown or z bits in the operands, the expression
takes a value x.
 Equality Operators
• Equality operators are
– logical equality (==), logical inequality (!=), case
equality (===), and case inequality (!==).
• When used in an expression, equality operators
return
– Logical value 1 if true,
– Logical value 0 if false.
• These operators compare the two operands bit by
bit, with zero filling if the operands are of unequal
length
Note:
• The logical equality operators (==, !=) will yield an x if either operand has x or z in
its bits.
• However, the case equality operators ( ===, !== ) compare both operands bit by
bit and compare all bits, including x and z.
• The result is 1 if the operands match exactly, including x and z bits.
• The result is 0 if the operands do not match exactly.
• Case equality operators never result in an x.
Case Vs logical equality operators
 Bitwise operators
• Bitwise operators are negation (~), and(&), or (|),
xor (^), xnor (^~, ~^).
• Bitwise operators perform a bit-by-bit operation on
two operands.
• They take each bit in one operand and perform the
operation with the corresponding bit in the other
operand.
• If one operand is shorter than the other, it will be
bit-extended with zeros to match the length of the
longer operand.
Truth tables for bitwise operations
 Examples

Logical operators always yield a logical value 0, 1, x, whereas bitwise

operators yield a bit-by-bit value.
 Reduction operators
• Reduction operators are and (&), nand (~&), or (|), nor (~|), xor (^), and
xnor (~^, ^~).
• Reduction operators take only one operand.
• Reduction operators perform a bitwise operation on a single vector
operand and yield a 1-bit result.
• Bitwise operations are on bits from two different operands, whereas
reduction operations are on the bits of the same operand.
 Shift Operators
• Shift operators are right shift ( >>), left shift (<<),
arithmetic right shift (>>>), and arithmetic left shift (<<<).
• Regular shift operators shift a vector operand to the right
or the left by a specified number of bits.
• The operands are the vector and the number of bits to
shift.
• When the bits are shifted, the vacant bit positions are
filled with zeros.
 Concatenation Operator
• The concatenation operator ( {, } ) provides a mechanism to
append multiple operands.
• The operands must be sized.
• Unsized operands are not allowed because the size of each
operand must be known for computation of the size of the
result.
 Replication Operator
• Repetitive concatenation of the same number can be
expressed by using a replication constant.
• A replication constant specifies how many times to
replicate the number inside the brackets ( { } ).
 Conditional Operator
• The conditional operator(?:) takes three operands:
– Usage: condition_expr ? true_expr : false_expr ;
• The condition expression (condition_expr) is first
evaluated.
– If the result is true (logical 1), then the true_expr is
evaluated.
– If the result is false (logical 0), then the false_expr is
evaluated.
– If the result is x (ambiguous), then both true_expr and
false_expr are evaluated and their results are compared,
bit by bit, to return for each bit position and x if the bits
are different and the value of the bits if they are the same.
The action of a conditional operator is similar to a multiplexer. Alternately, it can
be compared to the if-else expression.
 Behavioral modeling
• Two basic statements in behavioral modeling is initial
and always
• BM has a procedural block that defines
– A region of code containing sequential statements.
• Two types of procedural blocks in Verilog
– The “always” block
– The “initial” block
• Each always and initial statement represents a separate
activity flow in Verilog.
• Each activity flow starts at simulation time 0.
 always
• Starts at zero simulation time
• Executes continuously in a looping manner
• Only “reg” type variables can be assigned
within an “always” block
• Models a block of activity that is repeated
continuously in a digital circuit
• Begin-end is used to build initial blocks similar
to {..} in C
 initial
• Stars at zero simulation time
• Executes only once during a simulation
• All initial blocks executed concurrently at time
0
• Begin-end is used to build initial blocks similar
to {..} in C
• Used for initialization, monitoring..
• Executed once at the beginning of simulation
(used in Test-benches)
initial blocks
Example – Behavioral modeling
module practice (y, a, b); //module definition
input a, b; // by default it takes 1 bit
output y; // one bit output
always @ (a,b)
begin
case ({a,b})
2’b00: y=1’b0;
2’b01: y=1’b0;
2’b10: y=1’b0;
2’b11: y=1’b1;
endcase
end
endmodule
 Procedural assignments
• Two types – blocking (uses “=“) and nonblocking (uses “<=“)
• Procedural assignment statement assign values to reg, integer,
real or time variables.
• It cannot assign values to nets (wire data types).
• Registers (reg data type) can be assigned the value of net (wire),
constant, another register or specific value.

Syntax:
variable_lvalue = [timing_control] expression
variable_lvalue <= [timing_control] expression
[timing_control] variable_lvalue = expression
[timing_control] variable_lvalue <= expression
 Blocking assignments
• Are executed in the order they are coded. Hence they
are sequential.
• Since they block the execution of next statement , till
the current statement is executed , they are called
blocking assignments.
// blocking assignments
initial begin
x = #5 1'b0; // at time 5
y = #3 1'b1; // at time 8
z = #6 1'b0; // at time 14
end
 Nonblocking assignments
• They are executed in parallel.
• Since execution of next statement is not blocked due
to the execution of current statement .
• Therefore they are called as non-blocking assignment.
reg x, y, z;
// nonblocking assignments
initial begin
x <= #5 1'b0; // at time 5
y <= #3 1'b1; // at time 3
z <= #6 1'b0; // at time 6
end
 Statements
• Control/conditional statements
• If and If-else statements
• Case statements
– Casex and casez statements
• Loop statements
– Forever, repeat, while, for
 Control/ Conditional statement
//Type 1 conditional statement. No else statement.
//Statement executes or does not execute.
if () true_statement ;

//Type 2 conditional statement. One else statement

//Either true_statement or false_statement is evaluated
if () true_statement ;
else false_statement ;

//Type 3 conditional statement. Nested if-else-if.

//Choice of multiple statements. Only one is executed.
if () true_statement1 ;
else if () true_statement2 ;
else if () true_statement3 ;
else default_statement ;
 Case statement
case (expression)
alternative1: statement1;
alternative2: statement2;
alternative3: statement3;
...
...
default: default_statement;
endcase
 4-to-1 MUX
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0; reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0}) //Switch based on concatenation of control signals
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
2'd3 : out = i3;
default: $display("Invalid control signals");
endcase
endmodule
 Casex and casez
• There are two variations of the case statement
– casex and casez.
– casez treats all z values in the case alternatives or
the case expression as don't cares. All bit positions
with z can also be represented by ? in that
position.
– casex treats all x and z values in the case item or
the case expression as don't cares
 Loop statement
• There are four types of looping statements in
Verilog:
– while, for, repeat, and forever
• All looping statements can appear only inside an
initial or always block. Loops may contain delay
expressions.
• While loop: The while loop executes until the while
expression is not true. If the loop is entered when
the while-expression is not true, the loop is not
executed at all.
while
 For loop
• The for loop contains three parts:
– • An initial condition
– • A check to see if the terminating condition is
true
– • A procedural assignment to change value of the
control variable
 repeat
• Executes the loop a fixed number of times
• Must contain a number (constant, variable, signal value)
• Variable or signal value evaluated only when the loop
starts
 Forever loop
• No expression
• Executes forever until $finish is executed
• Can also be exited using disable
• Useful to generate a clock in test benches
 Procedural Blocks
 If procedural block contains more than one
statement, then those statements are enclosed within….
 Sequential begin-end block
 Parallel fork-join block
 when using begin-end we can give name to that
group called as named blocks.
All statements are executed All statements are executed
sequentially. Parallel.
Sequential Statement Groups:

Parallel Statement Groups:

 Timing control
• Delay Timing Control
 Regular delay control
 Intra assignment delay control

• Event Timing control

 Edge-triggered event control
 Named event control
 Event or control
 Level-sensitive event control
 Regular delay control
• Defers (postponed) the execution of the entire
statement

reg x, y;
integer count;
#25 y <= ~x; // at time 25
#15 count <= count + 1; // at time 40
 Intra assignment delay control
• Defers the assignment to the left-hand-side
variable
y=#25 ~x; // assign to y at time 25
count = #15 count + 1; // assign to count at time 40

y <= #25 ~x; // assign to y at time 25

count <= #15 count + 1; // assign to count at time 15
Edge triggered event control
Edge-triggered event control
 @(posedge clock)
 @(negedge clock)
always @(posedge clock) begin
reg1 <= #25 in_1;
reg2 <= @(negedge clock) in_2 ^ in_3;
reg3 <= in_1;
end
 Named event control

event received_data; // declare

always @(posedge clock)
if (last_byte) -> received_data; // trigger
always @(received_data) // recognize
begin ... end
 Event or control
Event or Control
Event or control
 or
 ,
 * or (*) means any signals.

always @(posedge clock or negedge reset_n)

if (!reset_n) q <= 1`b0;
else q <= d;
 Level sensitive event control

always
wait (count_enable) count = count –1 ;
always
wait (count_enable) #10 count = count –1 ;
 2-4 decoder – Behavioral modeling
module two-four-decoder(data_in, data-out);
input [1:0]data_in;
output [3:0]data_out;
reg [3:0] data_out;
always @(data_in)
case (data_in)
2’b00 : data_out = 4’b0001;
2’b01 : data_out = 4’b0010;
2’b10 : data_out = 4’b0100;
2’b11 : data_out = 4’b1000;
endcase
endmodule
 3-to-8 decoder
module three-eight-decoder(data_in, data_out);
input [2:0]data_in;
output [7:0]data_out;
reg [7:0] data_out;
always @(data_in)
case (data_in)
3’b000 : data_out = 8’b00000001;
3’b001 : data_out = 8’b00000010;
3’b010 : data_out = 8’b00000100;
3’b011 : data_out = 8’b00001000;
3’b100 : data_out = 8’b00010000;
3’b101 : data_out = 8’b00100000;
3’b110 : data_out = 8’b01000000;
3’b111 : data_out = 8’b10000000;
endcase
endmodule