Multiprocessors architecture

Why Choose a Multiprocessor?

• A single CPU can not go so fast, use more
than one CPU to improve performance

• Multiple users

• Multiple applications

• Multi-tasking within an application

• Responsiveness and/or throughput

• Share hardware between CPUs

 Multiprocessor Symmetry
• In a multiprocessing system, all CPUs may be equal, or
some may be reserved for special purposes.
• A combination of hardware and operating-system
software design considerations determine the symmetry.

• Systems that treat all CPUs equally are called symmetric

multiprocessing (SMP) systems.
• If all CPUs are not equal, system resources may be
divided in a number of ways, including asymmetric
multiprocessing (ASMP), non-uniform memory access
(NUMA) multiprocessing, and clustered multiprocessing.
 Instruction and Data Streams
Multiprocessors can be used in different ways:
• Uniprossesors (single-instruction, single-data or SISD)
• Within a single system to execute multiple, independent
sequences of instructions in multiple contexts (multiple-
instruction, multiple-data or MIMD);
• A single sequence of instructions in multiple contexts
(single-instruction, multiple-data or SIMD, often used in
vector processing);
• Multiple sequences of instructions in a single context
(multiple-instruction, single-data or MISD, used for
redundancy in fail-safe systems and sometimes applied
to describe pipelined processors).
 Processor Coupling
Tightly-coupled multiprocessor systems:
• Contain multiple CPUs that are connected at the bus level.
• These CPUs may have access to a central shared memory
(Symmetric Multiprocessing, or SMP), or may participate in a
memory hierarchy with both local and shared memory (Non-
Uniform Memory Access, or NUMA).
• Example: IBM p690 Regatta, Chip multiprocessors, also
known as multi-core computing.

Loosely-coupled multiprocessor systems:

• Often referred as clusters
• Based on multiple standalone single or dual processor
commodity computers interconnected via a high speed
communication system, such as Gigabit ethernet.
• Example: Linux Beowulf cluster
 Multiprocessor Communication
Architectures
Message Passing
• Separate address space for each processor
• Processors communicate via message passing
• Processors have private memories
• Focuses attention on costly non-local operations

Shared Memory
• Processors communicate with shared address space
• Processors communicate by memory read/write
• Easy on small-scale machines
• Lower latency
• SMP or NUMA
 Shared-Memory Processors
• Single copy of the OS (although some parts might be
parallel)
• Relatively easy to program
• Difficult to scale to large numbers of processors
processor
1
processor
2
... processor
N

cache cache cache

interconnection network

memory
1
memory
2
... memory
M

UMA machine block diagram

Types of Shared-Memory Architectures
UMA
• Uniform Memory Access
• Access to all memory occurred at the same speed for
all processors.
• We will focus on UMA today.
NUMA
• Non-Uniform Memory Access
• “Distributed Shared Memory”.
• Typically interconnection is grid or hypercube.
• Access to some parts of memory is faster for some
processors than other parts of memory.
• Harder to program, but scales to more processors
 Bus Based UMA
(a) Simplest MP:
More than one processor on a single bus
connect to memory, bus bandwidth becomes
a bottleneck.
(b) Each processor has a cache to reduce the need
to access to memory.
(c) To further scale the number of processors, each
processor is given private local memory.
 NUMA
• All memories can be addressed by all processors, but access to a
processor’s own local memory is faster than access to another
processor’s remote memory.
• Looks like a distributed machine, but the interconnection network is
usually custom-designed switches and/or buses.
 OS Option 1
Each CPU has its own OS
• Statically allocate physical memory to each CPU
• Each CPU runs its own independents OS
• Share peripherals
• Each CPU handles its processes system calls
• Used in early multiprocessor systems
• Simple to implement
• Avoids concurrency issues by not sharing
• Issues: 1. Each processor has its own scheduling queue.
2. Each processor has its own memory partition.
3. Consistency is an issue with independent disk buffer caches and
potentially shared files.
 OS Option 2
Master-Slave Multiprocessors
• OS mostly runs on a single fixed CPU.
• User-level applications run on the other CPUs.
• All system calls are passed to the Master CPU for processing
• Very little synchronisation required
• Single to implement
• Single centralised scheduler to keep all processors busy
• Memory can be allocated as needed to all CPUs.
• Issues: Master CPU becomes the bottleneck.
 OS Option 3
Symmetric Multiprocessors (SMP)
• OS kernel runs on all processors, while load and resources are balanced
between all processors.
• One alternative: A single mutex (mutual exclusion object) that make the
entire kernel a large critical section; Only one CPU can be in the kernel at a
time; Only slight better than master-slave
• Better alternative: Identify independent parts of the kernel and make each of
them their own critical section, which allows parallelism in the kernel
• Issues: A difficult task; Code is mostly similar to uniprocessor code; hard
part is identifying independent parts that don’t interfere with each other
Interconnection Networks
Multiprocessors interconnection networks (INs) can be
classified based on a number of criteria. These include
(1) Mode of operation (synchronous versus asynchronous),
(2) Control strategy (centralized versus decentralized),
(3) Switching techniques (circuit versus packet),
(4) Topology (static versus dynamic).

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 Mode of Operation

• According to the mode of operation, INs are

classified as synchronous versus asynchronous. In
synchronous mode of operation, a single global
clock is used by all components in the system such
that the whole system is operating in a lock–step
manner. Asynchronous mode of operation, on the
other hand, does not require a global clock.
Handshaking signals are used instead in order to
coordinate the operation of asynchronous systems.
While synchronous systems tend to be slower
compared to asynchronous systems, they are race
and hazard-free.
2- Control Strategy

According to the control strategy, INs can be classified as centralized versus

decentralized. In centralized control systems, a single central control unit is used to
oversee and control the operation of the components of the system. In decentralized
control, the control function is distributed among different components in the
system.
3- Switching Techniques
Interconnection networks can be classified according to the switching mechanism
as circuit versus packet switching networks. In the circuit switching mechanism, a
complete path has to be established prior to the start of communication between a
source and a destination.
. In a packet switching mechanism, communication between a source and
destination takes place via messages that are divided into smaller entities, called
packets. On their way to the destination, packets can be sent from a node to
another in a store-and-forward manner until they reach their destination. While
packet switching tends to use the network resources more efficiently compared to
circuit switching, it suffers from variable packet delays.

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4- Topology
An interconnection network topology is a mapping function from the set
of processors and memories onto the same set of processors and
memories. In other words, the topology describes how to connect
processors and memories to other processors and memories. A fully
connected topology, for example, is a mapping in which each processor is
connected to all other processors in the computer. A ring topology is a
mapping that connects processor k to its neighbors, processors (k - 1) and
(k 1 +).
In general, interconnection networks can be classified as static versus
dynamic networks. In static networks, direct fixed links are established
among nodes to form a fixed network, while in dynamic networks,
connections are established as needed. Switching elements are used to
establish connections among inputs and outputs.

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 Shared memory interconnection networks.
(a) bus-based and (b) switch-based shared memory
systems

bus-based systems when a single bus is used versus 18

the case when multiple buses are used
Examples of static topologies.

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 dynamic INs: (a) single-stage, (b) multistage,

The omega MIN connects eight sources to eight destinations. The

connection from the source 010 to the destination 010 is shown as a
bold path.

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 Conclusion
• Parallel processing is a future technique for
higher performance and effectiveness for multi
programmed workloads.
• MPs combine the difficulties of building complex
hardware systems and complex software
systems.
• Communication, memory, affinity and
throughputs presents an important influence on
the systems costs and performances
• On-chip MPs technology appears to be growing
Thank you