Vidyavardhaka College of Engineering, Mysuru

Autonomous Institute, Affiliated to VTU

Accredited by NBA | NAAC with ‘A’ Grade

Module – 1

Introduction to ARM Microcontrollers

 Presentation Outline
Syllabus

Introduction

Thumb-2 Technology

ARM CORTEX M3 Architecture

Operation Modes, Interrupts and Exceptions

Stack, Reset Sequence and Memory Map

 Syllabus

Syllabus
Thumb-2 technology and applications of ARM, Architecture of ARM cortex
M3, Various units in the architecture, Debugging support, General purpose
Registers, Special Registers, Exceptions, Interrupts, stack operation, Reset
Sequence
Self Study Components
Reset Sequence

Textbook: Joseph Yiu, "The Definitive Guide to ARM Cortex-M3", Second

Edition, Newness, (Elsevier), 2010

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 Introduction
• ARM stands for Advanced RISC Machine (originally Acorn RISC Machine)

• Developed by ARM Ltd : British Semiconductor and Software design company based in
Cambridge, England
• Joint venture: Acorn Computers, Apple and VLSI technology in 1990

• CORTEX M3 released in 2006

• 32-bit microcontrollers
• Excellent performance at low gate count
• Greater performance efficiency: More work without increasing frequency/power
• Lower power consumption
• Enhanced determinism
• Improved code density
• Ease of use
• Low cost solutions
• Wide choice of development tools
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 Thumb-2 Technology
Extension of Thumb Instruction Set Architecture

Instructions: old 16-bit + new 16-bit + new 32 bit

More complex operations in Thumb state

Reduction of state switching between ARM and Thumb

Higher Efficiency

Cortex M3 uses only Thumb-2 IS for all operations

Cortex M3 is not backwards compatible

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 CORTEX M3 Processor Applications
• Low Cost Microcontrollers
• Consumer products: Toys to Electrical Appliances
• Low power and high performance: Enable Embedded Developers to migrate to 32 bit
platform
• Automotive
• Low Interrupt Latency – Use in real time
• Built in Nested Vectored Interrupt Controller (NVIC), 240 external interrupts
• Data communications
• Thumb-2 instruction set bit field manipulation: Ideal for Bluetooth and ZigBee
• Industrial control
• Key factors: simplicity, fast response and reliability
• Enhanced fault handling features
• Consumer products
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 CORTEX M3 Architecture
32 bit Microprocessor
32-bit data path, register bank &
memory interfaces

Harvard Architecture: separate

instruction and data buses

Unified Memory System –

Instruction and Data bus share
same memory space

Memory Protection Unit and

Interrupt Controller

Debugging support

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 Registers
R0 to R15. R13 is banked with only 1 copy visible at any point of time

General Purpose Registers Stack Pointers Other Registers

• R0 to R12 • R13 is stack pointer • R14 is Link Register: Return

• Used for data operations • Two stack pointers address from subroutine
• Some 16-bit Thumb • Main Stack Pointer (MSP)
instructions can access only • Default • R15 is Program Counter
R0 to R7 • OS Kernel and Exception
handlers
• Process Stack Pointer (PSP)
• Application Code
• Word Aligned: Lowest 2 bits
are always 0

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 Special Registers
Can be accessed by only special instructions
• 5 Special Purpose Registers
• Program Status Registers (xPSR), Interrupt Mask Registers (PRIMASK, FAULTMASK,
BASEPRI, CONTROL) and Control Register

Functions of Special Registers

Arithmetic and Logic Processing Flags (Zero, Carry), execution status and current executing interrupt
xPSR
number

PRIMASK Disable all interrupts except Non Maskable Interrupts (NMI) and hard faults

FAULTMASK Disable all interrupts except the NMI

BASEPRI Disable all interrupts of specific or lower priority level

CONTROL Define privileged status and stack and stack pointer selection
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 Program Status Register
1 Application Program Status Register (APSR) MRS instruction to Read and Write

2 Interrupt Program Status Register (IPSR)

Read Only
3 Execution Program Status Register (EPSR)

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 Interrupt Mask Registers
• 1 bit register
PRIMASK • Allows only NMI and Hard Fault exception if set.
• Default value is 0

• 1 bit register
FAULTMASK • Allows only NMI if set.
• Interrupts and Fault handling exceptions are disabled. Default value is 0

• 8 bit register
BASEPRI • Defines masking priority levels.
• Disables all interrupts less than or equal to priority value if set

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 Control Register
2 bit register
• Writable only in a privileged state
Control [0] • 0 – Privileged in thread mode
• 1 – User state in thread mode

• Indicates Stack Status

Control [1] • 1 – Alternate Stack used
• 0 – Default Stack used

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 Operation Mode
• Two modes
• Thread Mode: Normal mode of operation
• Handler Mode: During interrupts, exceptions and faults
• Two privileges
• User Access Level: Access to system control space (SCS) (memory region for
configuration registers and debugging components are blocked). Instruction accessing
special registers except APSR are blocked. Fault exception occurs if tried
• Privileged Access Level

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 Operation Modes – Allowable Transition

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 Operation Mode

Switching of Operation Mode by Programming the Control Register or by Exceptions.

Simple Applications Do Not Require User Access Level in Thread Mode.

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 Interrupts and Exceptions
Interrupt is an event that forces the processor to stop executing the thread immediately
and execute ISR and then resume executing the thread

Main Program ISR

Instructions Instructions
Instructions Instructions
Instructions Instructions
..
..
..
.. Hardware Non
Instructions
..
Triggered Maskable
Interrupt
.. Interrupts Interrupts
..
Instructions Software
.. Maskable
.. Triggered
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 Interrupts and Exceptions

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 Interrupts and Exceptions
Vector Table

The vector table is an array of

word data inside the system
memory, each representing the
starting address of one
exception type. The vector
table is relocatable, and the
relocation is controlled by a
relocation register in the NVIC

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 Stack
• Stack is a linear data structure that stores elements with access restriction. Elements can be added or
removed from one end only
• Stack Pointer (SP) keeps track of contents of stack
• PUSH (Write to stack) and POP (Read from stack) are two
Stack Operations
• ARM Cortex M3 performs 32 bit PUSH and POP operations

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 Endianness
The order in which the computer memory stores the sequence
of bytes

Little Endian

Lower byte in lower

address

Bit Endian

Higher byte in
lower address

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 Reset Sequence
Reads two Words from Memory

• Address 0x00000000 : Starting value of R13 (the SP)

• Address 0x00000004 : Reset Vector (Starting address of
program execution; LSB should be 1 to indicate Thumb
State)

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 Memory Map

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