Chapter 1.

Basic Structure of
Computers
 Introduction
•Computers have become part and parcel of our daily lives.
–They are everywhere (embedded systems?)
–Laptops, tablets, mobile phones, intelligent appliances.

•It is required to understand how a computer works.

–What are there inside a computer?
–How does it work?

•We distinguish between two terms:

Computer Architecture and Computer Organization.
•Computer Organization:
–Design of the components and functional blocks using
which computer systems are built.
–Analogy: civil engineer’s task during building construction
(cement, bricks, iron rods, and other building materials).

•Computer Architecture:
–How to integrate the components to build a computer
system to achieve a desired level of performance.
–Analogy: architect’s task during the planning of a building
(overall layout, floorplan, etc.).
 Functional Units
Arithmetic
Input and
logic

Memory

Output Control

I/O Processor

Figure 1.1. Basic functional units of a computer.

 Information Handled by a Computer
• Instructions/machine instructions
 Govern the transfer of information within a computer as well
as between the computer and its I/O devices
 Specify the arithmetic and logic operations to be performed
 Program

• Data
 Used as operands by the instructions
 Source program
 Memory Unit
• Store programs and data
–Two main types of memory subsystems.
•Primary or Main memory, which stores the active instructions
and data for the program being executed on the processor.
•Secondary memory, which is used as a backup and stores all
active and inactive programs and data, typically as files.
–The processor only has direct access to the primary memory.
 –In reality, the memory system is implemented as a
hierarchy of several levels.
•Registers, cache, primary memory, secondary memory.
•Objective is to provide faster memory access at affordable
cost.

–Various types of memory are possible.

a)Random Access Memory (RAM)

 which is used for the cache and primary memory sub-systems.
Read and Write access times are independent of the location
being accessed.
b)Read Only Memory (ROM), which is used as part of the
primary memory to store some fixed data that cannot be
changed.

c)Magnetic Disk
which uses direction of magnetization of tiny magnetic
particles on a metallic surface to store data.
Access times vary depending on the location being
accessed, and is used as secondary memory.

d)Flash Memory
which is replacing magnetic disks as secondary memory
devices.
They are faster, but smaller in size as compared to disk.
 Inside the Processor
–Also called Central Processing Unit (CPU).
–Consists of a Control Unit and an Arithmetic Logic Unit (ALU).
•All calculations happen inside the ALU.
•The Control Unit generates sequence of control signals to carry
out all operations.
–The processor fetches an instruction from memory for execution.
•An instruction specifies the exact operation to be carried out.
•It also specifies the data that are to be operated on.
•A program refers to a set of instructions that are required to
carry out some specific task (e.g. sorting a set of numbers).
What is the role of ALU?

–It contains several registers, some general-purpose and some

special- purpose, for temporary storage of data.
–It contains circuitry to carry out logic operations, like AND,
OR, NOT, shift, compare, etc.
–It contains circuitry to carry out arithmetic operations like
addition, subtraction, multiplication, division, etc.
What is the role of control unit?
–Acts as the nerve center that senses the states of various
functional units and sends control signals to control their states.
–To carry out a specific operation (say, R1 <- R2 + R3), the control
unit must generate control signals in a specific sequence.
•Enable the outputs of registers R2 and R3.
•Select the addition operation.
•Store the output of the adder circuit into register R1.
–When an instruction is fetched from memory, the operation
(called opcode) is decoded by the control unit, and the control
signals issued
 Input Unit
• Used to feed data to the computer system from the external
environment.

–Data are transferred to the processor/memory after

appropriate encoding.

• Common input devices:

–Keyboard
–Mouse
–Camera
 Output Unit
• Used to send the result of some computation to the outside
world.
• Common output devices:
–LCD/LED screen
–Printer and Plotter
–Speaker / Buzzer
–Projection system
Basic Operational Concepts
 Review
• Activity in a computer is governed by instructions.
• To perform a task, an appropriate program consisting of
a list of instructions is stored in the memory.
• Individual instructions are brought from the memory
into the processor, which executes the specified
operations.
• Data to be used as operands are also stored in the
memory.
 A Typical Instruction
• Add LOCA, R0
 Add the operand at memory location LOCA to the operand
in a register R0 in the processor.
 Place the sum into register R0.
 The original contents of LOCA are preserved.
 The original contents of R0 is overwritten.
 Instruction is fetched from the memory into the processor
 – the operand at LOCA is fetched and added to the
contents of R0
 – the resulting sum is stored in register R0.
 Separate Memory Access and ALU
Operation
• Load LOCA, R1
• Add R1, R0
• Whose contents will be overwritten?
Connection Between the Processor and the Memory
Memory

MAR MDR
Control

PC R0

R1
Processor
IR

ALU
Rn - 1

n general purpose
registers

Figure 1.2. Connections between the processor and the memory.

 Registers
• Instruction register (IR)
• Program counter (PC)
• General-purpose register (R0 – Rn-1)
• Memory address register (MAR)
• Memory data register (MDR)
 For Interfacing with the Primary Memory

•Two special-purpose registers are used:

–Memory Address Register (MAR): Holds the address of the
memory location to be accessed.
–Memory Data Register (MDR): Holds the data that is being
written into memory, or will receive the data being read out from
memory.

M
A
R

PROCESSOR PRIMARY
M
MEMORY
D
R

Control Signals
•Memory considered as a linear array of storage locations
(bytes or words) each with unique address.

•To read data from memory

a)Load the memory address into MAR.
b)Issue the control signal READ.
c)The data read from the memory is stored into MDR.

•To write data into memory

a)Load the memory address into MAR.
b)Load the data to be written into MDR.
c)Issue the control signal WRITE.
For Keeping Track of Program / Instructions
•Two special-purpose registers are used:

–Program Counter (PC): Holds the memory address of the next

instruction to be executed.
•Automatically incremented to point to the next instruction when
an instruction is being executed.

–Instruction Register (IR): Temporarily holds an instruction that

has been fetched from memory.
•Need to be decoded to find out the instruction type.
•Also contains information about the location of the data.
 Typical Operating Steps
• Programs reside in the memory through input devices
• PC is set to point to the first instruction
• The contents of PC are transferred to MAR
• A Read signal is sent to the memory
• The first instruction is read out and loaded into MDR
• The contents of MDR are transferred to IR
• Decode and execute the instruction
 Typical Operating Steps (Cont’)
• Get operands for ALU
 General-purpose register
 Memory (address to MAR – Read – MDR to ALU)

• Perform operation in ALU

• Store the result back

 To general-purpose register
 To memory (address to MAR, result to MDR – Write)

• During the execution, PC is incremented to the next

instruction
 Example Instructions
• We shall illustrate the process of instruction execution with
the help of the following two instructions:

a)ADD LOCA, R1
• Add the contents of memory location LOCA (i.e. address of
the memory location is LOCA) to the contents of register R1.
• R1  R1 + Mem[LOCA]

b)ADD R1, R2
• Add the contents of register R2 to the contents of register
R1.
• R2  R1 + R2
Execution of ADD LOCA, R1
•Assume that the instruction is stored in memory location 1000,
the initial value of R1 is 50, and LOCA is 5000.
• Before the instruction is executed, PC contains 1000. PC=1000
• Content of PC is transferred to MAR. MAR  PC
• READ request is issued to memory unit.
• The instruction is fetched to MDR. MDR <- Mem[MAR]
• Content of MDR is transferred to IR. IR <- MDR
• PC is incremented to point to the next instruction. PC <-PC + 4
• The instruction is decoded by the control unit.

1000 ADD R1 5000

• LOCA (i.e. 5000) is transferred (from IR) to MAR. MAR IR[Operand]
• READ request is issued to memory unit.
• The data is fetched to MDR. MDR Mem[MAR]
• The content of MDR is added to R1. R1 R1 + MDR

The steps being carried out are called micro-operations:

MAR PC
MDR Mem[MAR]
IR MDR
PC PC + 4
MAR IR[Operand]
MDR Mem[MAR]
R1 R1 + MDR
 Interrupt
• Normal execution of programs may be preempted if some
device requires urgent servicing.
• The normal execution of the current program must be
interrupted – the device raises an interrupt signal.
• Interrupt-service routine

• Current system information backup and restore (PC, general-

purpose registers, control information, specific information)
 Bus Structures
• There are many ways to connect different parts inside a
computer together.
• A group of lines that serves as a connecting path for
several devices is called a bus.
• Address/data/control
• The simplest way to connect the functional unit is to use
the single bus architecture.
–Only one data transfer allowed in one clock cycle.
–For multi-bus architecture, parallelism in data transfer is
allowed.
 Bus Structure
• Single-bus

Input Output Memory Processor

Figure 1.3. Single-bus structure.

 Speed Issue
• Different devices have different transfer/operate
speed.
• If the speed of bus is bounded by the slowest
device connected to it, the efficiency will be very
low.
• How to solve this?
• A common approach – use buffers.
 Performance
• The most important measure of a computer is
how quickly it can execute programs.
• Three factors affect performance:
 Hardware design
 Instruction set
 Performance
• The total to execute a program in figure is t5-
t0 this elapsed time, i.e, measure of
performance of entire computer system
• Performance of the processor is only the
periods during which processor is active.
These are the periods labelled program and
OS routines
Performance
 Performance
• Processor time to execute a program depends on the hardware involved in the execution of individual
machine instructions.
• The hardware comprises the processor and memory, which are connected by a bus as in fig 1.5
 Performance
• At the start of execution, all program instructions and
the required data are stored in the main memory.
• As the execution proceeds, instructions are fetched one
by one over the bus into the processor, and a copy is
placed in the cache later if the same instruction or data
item is needed a second time, it is read directly from the
cache.
• The processor and a relatively small cache memory can
be fabricated on a single integrated circuit chip.
 Performance
• A program will be executed faster if the movement of
instructions and data between the main memory and
the processor is minimized, which is achieved by using
the cache.
• For example:- Suppose a number of instructions are
executed repeatedly over a short period of time as
happens in a program loop.
 Processor Clock
• Processor circuits are controlled by a timing
signal called clock.
• The clock defines the regular time intervals
called clock cycles.
• To execute a machine instruction the processor
divides the action to be performed into a
sequence of basic steps that each step can be
completed in one clock cycle.
 Processor Clock
• The length P of one clock cycle is an important
parameter that affects the processor
performance.
• The execution of each instruction is divided into
several steps, each of which completes in one
clock cycle.
• Hertz – cycles per second
 Basic Performance Equation
• T – processor time required to execute a program that has been
prepared in high-level language

• The compiler generates a machine language object program that

corresponds to the source program.

• N – number of actual machine language instructions needed to

complete the execution and is not necessarily equal to the
number of machine instructions in the object program. (note:
loop)
 Basic Performance Equation
• S – average number of basic steps needed to execute one machine
instruction. Each step completes in one clock cycle

• R – clock rate

• We must emphasize that N, S & R are not independent parameters changing

one may affect another.

• Performance of the processor improved, only if T value is reduced.

N S
T 
R
How to improve T?
 Pipeline and Superscalar Operation
• Instructions are not necessarily executed one after
another.
• The value of S doesn’t have to be the number of clock
cycles to execute one instruction.
• Pipelining – overlapping the execution of successive
instructions.
• Add R1, R2, R3
• The contents of R1 & R2 are first transferred to the inputs
of ALU.
• After the addition operation is performed, the sum is
transferred to R3.
• The processor can read the next instruction from the
memory, while the addition operation is being performed.
 Pipeline and Superscalar Operation
• In the ideal case if all instructions are overlapped to the
maximum degree possible the execution proceeds at the
rate of one instruction completed in each clock cycle.
• Individual instructions still require several clock cycles to
complete. But for the purpose of computing T, effective
value of S is 1.
• A higher degree of concurrency can be achieved if multiple
instructions pipelines are implemented in the processor.
• it becomes possible to start the execution of several
instructions in every clock cycle. This mode of operation is
called superscalar execution.
 Clock Rate
• There are two possibilities for increasing the clock rate ‘R’.
 Improving the IC technology makes logical circuit faster, which
reduces the time of execution of basic steps. This allows the clock
period P, to be reduced and the clock rate R to be increased.
 Reducing the amount of processing done in one basic step also
makes it possible to reduce the clock period P.
• Increases in R that are entirely caused by improvements in IC
technology affect all aspects of the processor’s operation equally
except the time to access the main memory.
 Performance Measurement
• the evaluation of ‘T’ is highly complex. Moreover the parameters like the clock
speed and various architectural features are not reliable indicators of the
expected performance.
• Measure computer performance using benchmark programs.
• The performance measure is the time taken by the computer to execute a given
bench mark.
• Initially some attempts were made to create artificial programs that could be
used as bench mark programs.
• But synthetic programs do not properly predict the performance obtained
when real application programs are run.
 Performance Measurement

• A non profit organization called SPEC- system

performance evaluation corporation selects and
publishes bench marks.
• The program selected range from game playing,
compiler, and data base applications
• the program is compiled under test, and the running
time on a real computer is measured. The same
program is also compiled and run on one computer
selected as reference.
 Performance Measurement

• This means that the computer under test is 50 times faster

 Number, Arithmetic Operations,
and Characters
Number System: The Basics
•We are accustomed to the so-called decimal number system.
– Ten digits :: 0,1,2,3,4,5,6,7,8,9
–Every digit position has a weight which is a power of 10.
–Base or radix is 10.
•Examples:
234 = 2 x 102 + 3 x 101 + 4 x 100
250.67 = 2 x 102 + 5 x 101 + 0 x 100 + 6 x 10-1 + 7 x 10-2
 Binary Number System
•Two digits: 0 and 1.
–Every digit position has a weight that is a power of 2.
–Base or radix is 2.
Binary to decimal conversion
•Examples:
110 = 1 x 22 + 1 x 21 + 0 x 20
101.01 = 1 x 22 + 0 x 21 + 1 x 20 + 0 x 2-1 + 1 x 2-2
101011  1x25 + 0x24 + 1x23 + 0x22 + 1x21 + 1x20 = 43
.0101  0x2-1 + 1x2-2 + 0x2-3 + 1x2-4 = .3125
(.0101)2 = (.3125)10
101.11  1x22 + 0x21 + 1x20 + 1x2-1 + 1x2-2 = 5.75
(101.11)2 = (5.75)10
Unsigned Binary Numbers
•An n-bit binary number can have 2n distinct combinations.
– For example, for n=3, the 8 distinct combinations are:
000, 001, 010, 011, 100, 101, 110, 111
(0 to 23-1 = 7 in decimal).

Number of bits (n) Range of Numbers

8 0 to 28-1 (255)

16 0 to 216-1 (65535)

32 0 to 232-1
(4294967295)
64 0 to 264-1
•An n-bit binary integer:

b b …bbb
n-1 n-2 2 1 0

•Equivalent unsigned decimal value :

D = bn-12n-1 + bn-22n-2 + … + b222 + b121 + b020

Each digit position has a weight that is some power of 2.

 Signed Integer
• 3 major representations:
Sign and magnitude
One’s complement
Two’s complement
• Assumptions:
4-bit machine word
16 different values can be represented
Roughly half are positive, half are negative
 (a) Sign-magnitude Representation
•For an n-bit number representation:
–The most significant bit (MSB) indicates sign
(0: positive, 1: negative).
–The remaining (n-1) bits represent the magnitude of the number.

bn-1 bn-2 b1 b0

Sign Magnitude
 Sign and Magnitude Representation
-7 +0
-6 1111 0000 +1
1110 0001
-5 +2 +
1101 0010
-4 1100 0011 +3 0 100 = + 4

-3 1011 0100 +4 1 100 = - 4

1010 0101
-2 +5 -
1001 0110
-1 1000 0111 +6
-0 +7

High order bit is sign: 0 = positive (or zero), 1 = negative

Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = -(2n-1 – 1) to + (2n-1 – 1)
Two representations for 0: +0: 0 00..000 and -0: 1 00..000
 (b) Ones Complement Representation

•Basic idea:
–Positive numbers are represented exactly as in sign-magnitude
form.
–Negative numbers are represented in 1’s complement form.

•How to compute the 1’s complement of a number?

–Complement every bit of the number (10 and 01).
–MSB will indicate the sign of the number (0: positive, 1: negative).
 Example for n=4
Decimal 1’s Decimal 1’s
complement complement
+0 0000 -7 1000
+1 0001 -6 1001
+2 0010 -5 1010
+3 0011 -4 1011
+4 0100 -3 1100
+5 0101 -2 1101
+6 0110 -1 1110
+7 0111 -0 1111

To find the representation of, say, -4, first note that

+4 = 0100
-4 = 1’s complement of 0100 = 1011
•Range of numbers that can be represented in 1’s complement:
Maximum :: + (2n-1 – 1)
Minimum :: - (2n-1 – 1)
•A problem:
Two different representations of zero.
+0  0 000….0
-0  1 111….1
•Advantage of 1’s complement representation:
–Subtraction can be done using addition.
–Leads to substantial saving in circuitry.
One’s Complement Representation
-0 +0
-1 1111 0000 +1
1110 0001
-2 +2 +
1101 0010
-3 1100 0011 +3 0 100 = + 4

-4 1011 0100 +4 1 011 = - 4

1010 0101
-5 +5 -
1001 0110
-6 1000 0111 +6
-7 +7

• Subtraction implemented by addition & 1's complement

• Still two representations of 0! This causes some problems
• Some complexities in addition
 (c) Two's Complement Representation
•Basic idea:
–Positive numbers are represented exactly as in sign-magnitude
form.
–Negative numbers are represented in 2’s complement form.

•How to compute the 2’s complement of a number?

–Complement every bit of the number (10 and 01), and then
add one to the resulting number.
–MSB will indicate the sign of the number (0: positive, 1: negative).
 Example for n=4
Decimal 2’s Decimal 2’s
complement complement
+0 0000 -8 1000
+1 0001 -7 1001
+2 0010 -6 1010
+3 0011 -5 1011
+4 0100 -4 1100
+5 0101 -3 1101
+6 0110 -2 1110
+7 0111 -1 1111

To find the representation of, say, -4, first note that

+4 = 0100
-4 = 2’s complement of 0100 = 1011 + 1
= 1100
•Range of numbers that can be represented in 2’s complement:
Maximum :: + (2n-1 – 1)
Minimum :: - 2n-1

•Advantage of 2’s complement representation:

–Unique representation of zero.
–Subtraction can be done using addition.
–Leads to substantial saving in circuitry.

•Almost all computers today use 2’s complement representation

for storing negative numbers.
Two’s Complement Representation
-1 +0
-2 1111 0000 +1
1110 0001
-3 +2 +
1101 0010
-4 1100 0011 +3 0 100 = + 4

-5 1011 0100 +4 1 100 = - 4

1010 0101
-6 +5 -
1001 0110
-7 1000 0111 +6
-8 +7

• Only one representation for 0

• One more negative number than positive number

Binary, Signed-Integer Representations

B V alues represented

Sign and
b3 b2b1b0 magnitude 1' s complement 2' s complement

0 1 1 1 +7 +7 + 7
0 1 1 0 +6 +6 + 6
0 1 0 1 +5 +5 + 5
0 1 0 0 +4 +4 + 4
0 0 1 1 +3 +3 + 3
0 0 1 0 +2 +2 + 2
0 0 0 1 +1 +1 + 1
0 0 0 0 +0 +0 + 0
1 0 0 0 - 0 -7 - 8
1 0 0 1 - 1 -6 - 7
1 0 1 0 - 2 -5 - 6
1 0 1 1 - 3 -4 - 5
1 1 0 0 - 4 -3 - 4
1 1 0 1 - 5 -2 - 3
1 1 1 0 - 6 - 1 - 2
1 1 1 1 - 7 -0 - 1

Figure 2.1. Binary, signed-integer representations.

 2’s-Complement Add and Subtract
Operations
Addition:
Add n-bit representation, ignore the carry-out from
MSB position. Answer to be in the range
-2n-1 to +2n-1 -1

Subtraction:
X-Y, perform the 2’s complement of Y and then add it
to X as in addition. Answer to be in the range
-2n-1 to +2n-1 -1
2’s-Complement Add and Subtract Operations

(a) 0010 ( + 2) (b) 0100 ( + 4)

+ 0011 ( + 3) + 1010 - 6
0101 ( + 5) 1110 - 2
(c) 1011 - 5 (d) 0111 ( + 7)
+ 1110 - 2 + 1101  - 3
1001 - 7 0100 ( + 4)
(e) 1101 - 3 1101
- 1001 - 7 + 0111
0100 ( + 4)
(f) 0010 ( + 2) 0010
- 0100 ( + 4) + 1100
1110  - 2
(g) 0110 ( + 6) 0110
- 0011 ( + 3) + 1101
0011 ( + 3)
(h) 1001  - 7 1001
- 1011 - 5 + 0101
1110  - 2
(i) 1001 - 7 1001
- 0001 ( + 1) + 1111
1000  - 8
(j) 0010 ( + 2) 0010
- 1101  - 3 + 0011
0101 ( + 5)

Figure 2.4. 2's-complement Add and Subtract operations.

 Overflow Conditions

5 0101 -7 1001
3 0011 -2 1100
-8 1000 7 10111
Overflow Overflow

5 0101 -3 1101
2 0010 -5 1011
7 0111 -8 11000
No overflow No overflow
When the result of arithmetic operation is outside the range,
then it is arithmetic Overflow
Memory Locations and Addresses
• Number and character operands, as well as
instructions, are stored in the memory of a
computer.
• Modern computers have word lengths that
typically range from 16 to 64 bits. If the word
length of a computer is 32 bits, a single word
can store a 32-bit 2’s complement number or
four ASCII characters
 Memory Locations and Addresses
n bits

• Memory consists of first word

many millions of second word

storage cells, each of

which can store 1 bit.
• Data is usually •
•
accessed in n-bit •
groups. n is called i th word
word length.

•
•
•
last word

Figure 2.5. Memory words.

 Memory Locations and Addresses

• 32-bit word length example

32 bits

b 31 b 30 b1 b0

•
•
•
Sign bit: b 31= 0 for positive numbers
b 31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

Memory Locations and Addresses

• To retrieve information from memory, either for one

word or one byte (8-bit), addresses for each location are
needed.
• A k-bit address memory has 2k memory locations, namely
0 – 2k-1, called memory space.
• 24-bit memory: 224 = 16,777,216 = 16MB
• 32-bit memory: 232 = 4GB
• 10-bit memory: 210 = 1KB
 Byte addressability

• Three basic information quantities to deal with: the bit, byte

and word. A byte is always 8 bits, but the word length typically
ranges from 16 to 64 bits.
• The most practical assignment is to have successive addresses
refer to successive byte locations in the memory – byte-
addressable memory.
• Byte locations have addresses 0, 1, 2, … If word length is 32 bits,
they successive words are located at addresses 0, 4, 8,…
 Big-Endian and Little-Endian Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of
the word
Little-Endian: opposite ordering. lower byte addresses are used for the less
significant bytes of the word
 Word alignment

• In the case of a 32-bit word length, natural word

boundaries occur at addresses 0, 4, 8, …, We say
that the word locations have aligned addresses
• if the word length is 16 (2 bytes), aligned words
begin at byte addresses 0,2,4,…, and for a word
length of 64 (23 bytes), aligned words begin at
bytes addresses 0,8,16 ….
 Access numbers, characters, and
character strings
• A number usually occupies one word.
• It can be accessed in the memory by specifying its
word address.
• Similarly, individual characters can be accessed by
their byte address.
• In many applications, it is necessary to handle
character strings of variable length.
• A special control character with the meaning “end of
string” can be used as the last character in the string.
 ASCII Codes
American Standard Code for Information
Interchange
 Addressing modes

• The different ways in which the location of an

operand is specified in an instruction are referred to
as addressing modes.
• Register mode - The operand is the contents of a
processor register; the name (address) of the register
is given in the instruction.
• Absolute mode or Direct mode– The operand is in a
memory location; the address of this location is given
explicitly in the instruction.
• Move LOC, R2
 Addressing modes
Immediate mode

• The operand is given explicitly in the

instruction.
Move #200, R0
Indirect mode – The effective address of the
operand is the contents of a register or
memory location whose address appears in
the instruction.
Addressing modes
Indirect mode
 Addressing modes
Index mode

INDEXING AND ARRAYS

• the effective address of the operand is
generated by adding a constant value to the
contents of a register.
•Register is referred to as index register
•EA = X + [Rj], X denotes the constant value
contained in the instruction and Ri is the name
of the register involved.
Addressing modes
Index mode
 Addressing modes
Relative mode
• The effective address is determined by the Index
mode using the program counter in place of the
general-purpose register Ri.
• We have defined the Index mode using general-
purpose processor registers.
• PC, is used instead of a general purpose register.
Then, X(PC) can be used to address a memory
location that is X bytes away from the location
presently pointed to by the program counter.
 ACCESSING I/O DEVICES

• A simple arrangement to connect I/O devices to a

computer is to use a single bus arrangement. The bus
enables all the devices connected to it to exchange
information.
 ACCESSING I/O DEVICES
• Typically, it consists of three sets of lines used to carry
address, data, and control signals.
• Each I/O device is assigned a unique set of addresses.
• When the processor places a particular address on the
address line, the device that recognizes this address responds
to the commands issued on the control lines.
• The processor requests either a read or a write operation,
and the requested data are transferred over the data lines
• when I/O devices and the memory share the same address
space, the arrangement is called memory-mapped I/O.
 ACCESSING I/O DEVICES
• With memory-mapped I/O, any machine instruction that
can access memory can be used to transfer data to or from
an I/O device.
• For example, if DATAIN is the address of the input buffer
associated with the keyboard, the instruction
Move DATAIN, R0
Reads the data from DATAIN and stores them into
processor register R0.
the instruction Move R0, DATAOUT
Sends the contents of register R0 to location DATAOUT, which
may be the output data buffer of a display unit or a printer.
 ACCESSING I/O DEVICES

⚫ I/O devices and the memory may share the same address space:
Memory-mapped I/O.
⚫Any machine instruction that can access memory can be used to
transfer data to or from an I/O device.
.

⚫ I/O devices and the memory may have different address spaces:
I/O mapped I/O
⚫Special instructions to transfer data to and from I/O devices.
⚫I/O devices may have to deal with fewer address lines.
⚫In fact, address lines may be shared between I/O devices and
memory, with a control signal to indicate whether it is a memory
address or an I/O address.

86
 ACCESSING I/O DEVICES
Address lines
Bus Data lines
Control lines

Address Control Data and I/O

decoder circuits status registers int erface

•The hardware required to connect an I/O device to the bus.

Input device
•The address decoder enables the device to recognize its address when this address appears on the
address lines.
 ACCESSING I/O DEVICES
• The data register holds the data being transferred to
or from the processor. The status register contains
information relevant to the operation of the I/O
device.
• Both the data and status registers are connected to
the data bus and assigned unique addresses.
• The address decoder, the data and status registers,
and the control circuitry required to coordinate I/O
transfers constitute the device’s interface circuit.
 ACCESSING I/O DEVICES
• I/O devices operate at speeds that are vastly different from
that of the processor.
• An instruction that reads a character from the keyboard
should be executed only when a character is available in the
input buffer of the keyboard interface.
• For an input device a status flag, SIN is included as part of
the status register.
• The flag is set to 1 when character entered at the keyboard
and cleared to 0 once the character read by the processor.
• A similar procedure can be used in output operation using
SOUT flag bit
 EXAMPLE

• The flags KIRQ, DIRQ are used with interrupts.

 ACCESSING I/O DEVICES
Recall that the rate of transfer to and from I/O devices is
slower than the speed of the processor. This creates the need
for mechanisms to synchronize data transfers between them.
t
⚫Program-controlled I/O:
⚫Two other mechanisms used for synchronizing data
transfers between the processor and memory:
⚫ Interrupts.
⚫ Direct Memory Access.
 ACCESSING I/O DEVICES
• program-controlled I/O, in which the processor repeatedly
checks a status flag to achieve the required synchronization
between the processor and an input or output device. We say
that the processor polls the device.
• In the case of interrupts, synchronization is achieved by
having the I/O device send a special signal over the bus
whenever it is ready for a data transfer operation.
• Direct memory access is a technique used for high-speed I/O
devices. It involves having the device interface transfer data
directly to or from the memory, without continuous
involvement by the processor.
Interrupts
 Interrupts
• In program-controlled I/O, when the processor
continuously monitors the status of the device, it does
not perform any useful tasks.
• An alternate approach would be for the I/O device to alert the
processor when it becomes ready.
– Do so by sending a hardware signal called an interrupt to the
processor.
– At least one of the bus control lines, called an interrupt-request
line is dedicated for this purpose.
• Processor can perform other useful tasks while it is waiting for the
device to be ready.
 Interrupts (contd..)

Program 1 Interrupt Service

routine

Interrupt
occur i
sher
e i +1

M
•Processor is executing the instruction located at address i when an
interrupt occurs.
•Routine executed in response to an interrupt request is called the
interrupt-service routine.
•When an interrupt occurs, control must be transferred to the
interrupt service routine.
•But before transferring control, the current contents of the PC (i+1),
must be saved in a known
location.
•This will enable the return-from-interrupt instruction to resume
execution at i+1.
•Return address, or the contents of the PC are usually stored on the
processor stack.
 Interrupts (contd..)
⚫ Treatment of an interrupt-service routine is very similar to that of a
subroutine.
⚫ However there are significant differences:
⚫ A subroutine performs a task that is required by the calling program.
⚫ Interrupt-service routine and the program that it interrupts may
belong to different users.
⚫ As a result, before branching to the interrupt-service routine, not only
the PC, but other information such as condition code flags, and
processor registers used by both the interrupted program and the
interrupt service routine must be stored.
⚫ This will enable the interrupted program to resume execution upon
return from interrupt service routine.
 Interrupts (contd..)
⚫Saving and restoring information , Increases the total execution
time.
⚫ Saving and restoring information can be done automatically by the
processor or explicitly by program instructions.
⚫Saving and restoring registers involves memory transfers:
⚫the delay between the time an interrupt request is received, and the
start of execution of the interrupt-service routine. This delay is called
interrupt latency.
⚫ In order to reduce the interrupt latency, most processors save only the
minimal amount of information:
⚫This minimal amount of information includes Program Counter and
processor status registers.
⚫ Any additional information that must be saved, must be saved explicitly by
the program instructions at the beginning of the interrupt service routine.
 Interrupts (contd..)
• When a processor receives an interrupt-request, it must branch
to the interrupt service routine.
• It must also inform the device that it has recognized the
interrupt request.
• This can be accomplished in two ways:
– Some processors have an explicit interrupt-acknowledge
control signal for this purpose.
– In other cases, the data transfer that takes place between
the device and the processor can be used to inform the
device.
 Enabling & Disabling Interrupt
⚫ Interrupt-requests interrupt the execution of a program, and may alter
the intended sequence of events:
⚫ Sometimes such alterations may be undesirable, and must not be
allowed.
⚫ For example, the processor may not want to be interrupted by the
same device while executing its interrupt-service routine.
⚫ Processors generally provide the ability to enable and disable such
interruptions as desired.
⚫ One simple way is to provide machine instructions such as Interrupt-
enable and Interrupt-disable for this purpose.
⚫ To avoid interruption by the same device during the execution of an
interrupt service routine:
⚫ First instruction of an interrupt service routine can be Interrupt-
disable.
⚫ Last instruction of an interrupt service routine can be Interrupt-
enable.
 Interrupt: Handling Multiple devices
⚫ Multiple I/O devices may be connected to the processor and the
memory via a bus. Some or all of these devices may be capable of
generating interrupt requests.
⚫ Each device operates independently, and hence no definite order
can be imposed on how the devices generate interrupt requests?
⚫ How does the processor know which device has generated an
interrupt?
⚫ How does the processor know which interrupt service routine needs to
be executed?
⚫ When the processor is executing an interrupt service routine for one
device, can other device interrupt the processor?
⚫ If two interrupt-requests are received simultaneously, then how to
break the tie?
 Interrupt: Handling Multiple devices
⚫ Consider a simple arrangement where all devices send their interrupt-
requests over a single control line in the bus.
⚫ When the processor receives an interrupt request over this control line,
how does it know which device is requesting an interrupt?
⚫ This information is available in the status register of the device
requesting an interrupt:
⚫ The status register of each device has an IRQ bit which it sets to 1
when it requests an interrupt.
⚫ Interrupt service routine can poll the I/O devices connected to the bus.
The first device with IRQ equal to 1 is the one that is serviced.
⚫ Polling mechanism is easy, but time consuming to query the status bits of
all the I/O devices connected to the bus.
 Interrupt: Handling Multiple devices
• The device requesting an interrupt may identify itself directly to
the processor.
– Device can do so by sending a special code (4 to 8 bits) the
processor over the bus.
– Code supplied by the device may represent a part of the
starting address of the interrupt-service routine.
• Usually the location pointed to by the interrupting device is used
to store the starting address of the interrupt-service routine.
 Interrupt: Handling Multiple devices
⚫ How does the processor know which device has generated an
interrupt?
⚫ How does the processor know which interrupt service routine needs to
be executed?
⚫ When the processor is executing an interrupt service routine for one
device, can other device interrupt the processor?
⚫ If two interrupt-requests are received simultaneously, then how to
break the tie?
 Interrupt: Handling Multiple devices
⚫ Consider a simple arrangement where all devices send their interrupt-
requests over a single control line in the bus.
⚫ When the processor receives an interrupt request over this control line,
how does it know which device is requesting an interrupt?
⚫ This information is available in the status register of the device
requesting an interrupt:
⚫ The status register of each device has an IRQ bit which it sets to 1
when it requests an interrupt.
⚫ Interrupt service routine can poll the I/O devices connected to the bus.
The first device with IRQ equal to 1 is the one that is serviced.
⚫ Polling mechanism is easy, but time consuming to query the status bits
of all the I/O devices connected to the bus.
 Interrupt: Handling Multiple devices
– Device can do so by The device requesting an interrupt
may identify itself directly to the processor.
– ending a special code (4 to 8 bits) the processor over the bus.
– Code supplied by the device may represent a part of the starting address of the
interrupt-service routine.
• Usually the location pointed to by the interrupting device is
used to store the starting address of the interrupt-service
routine.
 Interrupt: Handling Multiple devices

⚫ before the processor started executing the interrupt service

routine for a device, it disables the interrupts from the device.
⚫ In general, same arrangement is used when multiple devices
can send interrupt requests to the processor.
⚫During the execution of an interrupt service routine of
device, the processor does not accept interrupt requests
from any other device.
 Interrupt: Handling Multiple devices
• Which devices can be allowed to interrupt a processor when it is executing an
interrupt service routine of another device?
• I/O devices are organized in a priority structure:
– An interrupt request from a high-priority device is accepted while the
processor is executing the interrupt service routine of a low priority device.
• A priority level is assigned to a processor that can be changed under program
control.
– Priority level of a processor is the priority of the program that is currently
being executed.
– When the processor starts executing the interrupt service routine of a device,
its priority is raised to that of the device.
– If the device sending an interrupt request has a higher priority than the
processor, the processor accepts the interrupt request.
 Interrupt: Handling Multiple devices
INTR1 I NTRp
Processor

Device Device Devic p

1 2 e

INTA1 INTA p

Priority
arbitration
•Each device has a separate interrupt-request and
interrupt-acknowledge line.
•Each interrupt-request line is assigned a different
priority level.
•Interrupt requests received over these lines are sent to a
priority arbitration circuit in the processor.
•If the interrupt request has a higher priority level than
the priority of the processor, then the request is
accepted.
 Interrupt: Handling Multiple devices

Polling scheme:

•If the processor uses a polling mechanism to poll the

status registers of I/O devices to determine which device
is requesting an interrupt.
•In this case the priority is determined by the order in
which the devices are polled.
•The first device with status bit set to 1 is the device
whose interrupt request is accepted.
Interrupt: Handling Multiple devices, Daisy chain scheme:

I NTR

Processor

Device 1 Device 2 Device n

INTA

•Devices are connected to form a daisy chain.

•Devices share the interrupt-request line, and interrupt-
acknowledge line is connected to form a daisy chain.
•When devices raise an interrupt request, the interrupt-
request line is activated.
•The processor in response activates interrupt-
acknowledge.
•Received by device 1, if device 1 does not need service, it
passes the signal to device 2.
•Device that is electrically closest to the processor has the
highest priority.
 •When I/O devices were organized into a priority structure,
each device had its own interrupt-request and interrupt-
acknowledge line.
•When I/O devices were organized in a daisy chain fashion, the
devices shared an interrupt-request line, and the interrupt-
acknowledge propagated through the devices.
•A combination of priority
I NTR1 structure and daisy chain scheme
can also used.
Device Device
INTA1
Processor

IN T R p

Device Device
INTA p
Priority arbitration
circuit
•Devices are organized into groups.
•Each group is assigned a different priority level.
•All the devices within a single group share an interrupt-
request line, and are connected to form a daisy chain.
Interrupt Hardware
 Exceptions
⚫ In general, the term exception is used to refer to any event that
causes an interruption.
⚫ Interrupt-requests from I/O devices is one type of an exception.
⚫ Other types of exceptions are:
⚫ Recovery from errors
⚫ Debugging
⚫ Privilege exception
 Exceptions
⚫ Many sources of errors in a processor. For example:
⚫ Error in the data stored.
⚫ Error during the execution of an instruction.
⚫ When such errors are detected, exception processing is initiated.
⚫ Processor takes the same steps as in the case of I/O interrupt-request.
⚫ It suspends the execution of the current program, and starts executing an
exception-service routine.
⚫ Difference between handling I/O interrupt-request and handling
exceptions due to errors:
⚫ In case of I/O interrupt-request, the processor usually completes the
execution of an instruction in progress before branching to the interrupt-
service routine.
⚫ In case of exception processing however, the execution of an instruction in
progress usually cannot be completed.
 Exceptions
• Certain instructions can be executed only when the processor is in
the supervisor mode. These are called privileged instructions.
• If an attempt is made to execute a privileged instruction in the user
mode, a privilege exception occurs.
• Privilege exception causes:
– Processor to switch to the supervisor mode,
– Execution of an appropriate exception-servicing routine.