UNIT III SYNCHRONOUS SEQUENTIAL LOGIC

Sequential Circuits - Storage Elements: Latches ,

Flip-Flops - Analysis of Clocked Sequential Circuits
- State Reduction and Assignment –Design
Procedure - Registers and Counters - HDL Models
of Sequential Circuits.
BLOCK DIAGRAM

A Z
External Combinational External
Input Logic Output

Y Y
Internal Input Internal Input
(present State) Memory (Next State)
DIFFERENCE BETWEEN COMBINATIONAL AND SEQUENTIAL CIRCUITS
S.No Combinational Circuits Sequential Circuits
1 Implemented using only Implemented using
logic gates Combinational Circuits and
memory elements

2 The output depends upon The output depends upon the

only the present input present input and previous
output
3 Behaviour is described by Behaviour is described by the
the set of output functions set of output functions and
next state(memory)

4 Example: Adder, subtractor, Example: Shift registers,

code convertor etc counters etc
TYPES of SEQUENTIAL CIRCUITS

Sequential Circuits

Synchronous Asynchronous
Sequential Circuits Sequential Circuits
Comparison Of Synchronous And Asynchronous Sequential Circuits
Synchronous Circuit Asynchronous Circuit
Synchronous sequential circuit is a The circuit in which the change in
system whose behaviour can be the input signal can affect memory
defined from the knowledge of the element at any instant of time.
signal at discrete instant of time.
The signal can affect the memory In this circuit, clock is absent and
element only at discrete instant of hence the state changes can occur
time. according to delay time of the logic.
Easier to design. More difficult to design.
Memory element are clocked flip Memory elements are either
flop. upclocked flip flop or time delay
elements
Latches
• Level Sensitive devices
• It is used for storing binary information.
High level
• Building blocks of Flip Flop.
Types Low level
• SR latch.
Falling edge
• D latch
Rising edge
SR Latch
S- Set
R-Reset
SR Latch(using NOR gate)

0 1

0 1
Truth Table

S R Q Q’
1 0 1 0
0 0 1 0 (after S=1,R=0)
0 1 0 1
0 0 0 1 (after S=0,R=1)
1 1 0 0 (for bidden)
SR Latch(using NAND gate)

0
Truth Table

S R Q Q’
1 0 0 1
1 1 0 1 (after S=1,R=0)
0 1 1 0
1 1 1 0 (after S=0,R=1)
0 0 1 1 (for bidden)
SR Latch Logic Diagram
Function Table

E S R Next State of Q
0 X X No change
1 0 0 No change
1 0 1 Q=0; reset state
1 1 0 Q=1; set state
1 1 1 Indeterminate
D latch

Function Table

E D Next State of Q
0 X No change
1 0 Q=0; reset state
1 1 Q=1; set state
Flip Flop(FF)
• It is memory storage element.
• It works on edge triggering.
Types of Edge Triggering
Positive Edge Triggering

Negative Edge Triggering

Types of Flip Flop
• SR Flip Flop
• D Flip Flop
• JK Flip Flop
• T Flip Flop
SR-Flip Flop

Logic Circuit Logic Symbol

S Q

CLK
Q’
R
Characteristic Table (Truth table)
S R Q(t+1)
0 0 Q(t) No change
0 1 0 Reset state
1 0 1 set state
1 1 Indeterminate

Characteristic Equation

Q(t+1)= S +QR’
D-Flip Flop

Logic Circuit Logic Symbol

Q
D

CLK Q’
Characteristic Table
D Q(t+1)
0 0 Reset state
1 1 Set state

Characteristic Equation

Q(t+1)= D
JK-Flip Flop

Logic Circuit Logic Symbol

J Q

CLK
Q’
K
Characteristic Table
J K Q(t+1)
0 0 Q(t) No change
0 1 0 Reset state
1 0 1 set state
1 1 Q’(t) Complement

Characteristic Equation

Q(t+1)= JQ’ +K’Q

T-Flip Flop

Logic Circuit Logic Symbol

Q
T

CLK Q’
Characteristic Table
T Q(t+1)
0 Q(t) No change
1 Q’(t) Complement

Characteristic Equation

Q(t+1)= TQ’+QT’=T
Excitation Table
JK-Flip Flop
Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
• T-Flip Flop

Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0
Registers:
• Used for storing binary information
• A group of flip-flops with common clock.
• Each flip-flop is capable of storing one bit of information.
Shift Registers:
• Logical configuration consists of chain of flip-flops.
• A register is capable of shifting the binary information held (stored) in each
cell to its neighbouring cell in a selected direction.(ie)Shift left or Shift right.
Types:
SISO-Serial In Serial Out shift register.
SIPO-Serial In Parallel Out shift register.
PIPO- Parallel In Parallel Out shift register.
PISO- Parallel In Serial Out shift register.
SISO-Serial In Serial Out shift register.

Din Qout
D Q1 D Q2 D Q3 D Q4

FF1 FF2 FF3 FF4

CLK

Figure shows the SISO shift register. It is implemented using 4 flip-flops. All
the flip-flops are applied with common clock signal. The data input is applied to
the FF1. The output of each flip-flop is applied as input to next flip-flop. The
output is obtained at the output of FF4.
SIPO-Serial In Parallel Out shift register.
Q1 Q2 Q3 Q4

Din
D Q1 x D Q2 x D Q3 x D Q4

FF1 FF2 FF3 FF4

CLK

Figure shows the SIPO shift register. It is implemented using 4 flip-flops. All
the flip-flops are applied with common clock signal. The data input is applied to
the FF1. The output of each flip-flop is applied as input to next flip-flop. The
output is obtained at the output of each flip-flop.
PIPO- Parallel In Parallel Out shift register.
Q1 Q3 Q4
Q2
D1 D2 D D3 D D4 D
D Q1 Q2 Q3 Q4

FF1 FF2 FF3 FF4

CLK

Figure shows the PIPO shift register. It is implemented using 4 flip-flops. All
the flip-flops are applied with common clock signal. The data input is applied
each the flip-flop and output is obtained at the output of each flip-flop.
PISO- Parallel In serial Out shift register.
• Figure shows the PISO shift register. It is implemented using 4 flip-flops. All the
flip-flops are applied with common clock signal.
• The data input is ANDed with Shift/Load signal and applied each flip-flop.
• When Shift/Load =1 or high the circuit will shift the data to next flip-flop.
• When Shift/Load =0 or low the data will be loaded to each flip-flop.
• The output is obtained at the output of the flip-flop FF4.
PIPO- Parallel In Parallel Out shift register.
Q1 Q2 Q3 Q4
D1 D2 D3 D4
D Q1 D Q2 D Q3 D Q4

FF1 FF2 FF3 FF4

CLK

Figure shows the PIPO shift register. It is implemented using 4 flip-flops. All
the flip-flops are applied with common clock signal. The data input is applied
each the flip-flop and output is obtained at the output of each flip-flop.
Counters:
Count a sequence of numbers in either up counter counts upwards or
down counter counts downwards. Sequence will be repeated.
Eg: Design a 3 bit synchronous counter using JK flipflop.
A B C JA KA JB KB JC KC
0 0 0 0 X 0 X 1 X
0 0 1 0 X 1 X X 1
0 1 0 0 X X 0 1 X
0 1 1 1 X X 1 X 1
1 0 0 X 0 0 X 1 X
1 0 1 X 0 1 X X 1
1 1 0 X 0 X 0 1 X
1 1 1 X 1 X 1 X 1
Excitation Table
JK-Flip Flop
Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Map for JA

B’C’ B’C BC BC’

A’ 0 1 3 2
1
A 4
x
5
x
7 6
x x

JA=BC

JA=BC
Map for KA

B’C’ B’C BC BC’

A’ 0 1 3 2
x x x x
A 4 5 7 6
1

KA =BC

KA=BC
Map for JB

B’C’ B’C BC BC’

A’ 0 1 3 2
1 x x
A 4 5 7 6
1 x x

JB=C

JB=C
Map for KB

B’C’ B’C BC BC’

A’ 0 1 3 2
x x 1
A 4
x
5
x
7
1
6

KB =C

KB=C
Map for JC

B’C’ B’C BC BC’

A’ 0 1 3 2
1 x x 1
A 4
1
5 7 6
x x 1

JC=1

JC=1
Map for KC

B’C’ B’C BC BC’

A’ 0 1 3 2
x
x 1 1
A 4
x
5
1
7
1
6
x

KC=1

KC=1
 J J
J
B C 1
A
K K
K

CLK

A B C
Design a 3 bit synchronous counter using T flipflop
A B C TA TB TC Q(t) Q(t+1) T
0 0 0 0 0 1 0 0 0
0 0 1 0 1 1 0 1 1
0 1 0 0 0 1 1 0 1
0 1 1 1 1 1 1 1 0
1 0 0 0 0 1
1 0 1 0 1 1
1 1 0 0 0 1
1 1 1 1 1 1
 B’C’ B’C BC BC’
A’ 0 1 3 2
1
A 4 5 7 6
1

TA=BC
 B’C’ B’C BC BC’
A’ 0 1 3 2
1 1
A 4 5 7 6
1 1

TB=C TC=1
 B T C T 1
A T

CLK

A B C
Asynchronous Counter
Asynchronous UP Counter

MSB
LSB 1
J 1 J Q J Q
1 Q
CLK
c B A
Q’ Q’ 1 K Q’
1 K 1 K

C B A
Characteristic Table
A B C CLK
J K Q(t+1)
0 0 0 0
0 0 Q(t)
0 0 1 1
0 1 0
1 0 1 0 1 0 2
1 1 Q’(t) 0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
0 0 0 8
Counter with unused states
Design a counter which count the following sequence 0,3,6,2,7,0…
draw the state diagram. Q(t) Q(t+1) T
0 0 0
A B C TA TB TC 0 1 1
0 0 0 0 1 1 1 0 1
0 1 1 1 0 1 1 1 0
1 1 0 1 0 0
0 1 0 1 0 1
1 1 1 1 1 1
000 011 110

111 010
Asynchronous Counter
Asynchronous DOWN Counter

LSB MSB
J 1 J Q 1 J Q
1 Q
CLK
c B A
Q’ Q’ 1 K Q’
1 K 1 K

C B A
Characteristic Table
A B C(LSB) CLK
J K Q(t+1)
0 0 0 0
0 0 Q(t)
1 1 1 1
0 1 0
1 1 0 2
1 0 1
1 0 1 3
1 1 Q’(t)
1 0 0 4
0 1 1 5
0 1 0 6
0 0 1 7
0 0 0 8
Mod-10/BCD counter
CLK Present State Next State
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0 0 1
1 0 0 0 1 0 0 1 0
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 1 0 0
4 0 1 0 0 0 1 0 1
5 0 1 0 1 0 1 1 0
6 0 1 1 0 0 1 1 1
7 0 1 1 1 1 0 0 0
8 1 0 0 0 1 0 0 1
9 1 0 0 1 1 0 1 0
10 1 0 1 0 1 0 1 1
1 T Q0 1 T Q1 1 T Q2 1 T Q3
CLK
1 2 3 4

Q0’ Q1’ Q2’ Q3’

R R R R
Mod-11 COUNTER
CLK Present State Next State
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0 0 1
1 0 0 0 1 0 0 1 0
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 1 0 0
4 0 1 0 0 0 1 0 1
5 0 1 0 1 0 1 1 0
6 0 1 1 0 0 1 1 1
7 0 1 1 1 1 0 0 0
8 1 0 0 0 1 0 0 1
9 1 0 0 1 1 0 1 0
10 1 0 1 0 1 0 1 1
1 T Q0 1 T Q1 1 T Q2 1 T Q3
CLK
1 2 3 4

Q0’ Q1’ Q2’ Q3’

R R R R
RING COUNTER/Straight Ring Counter
A ring counter is a circular shift register with only one flipflop set at a
particular time and all others are cleared using the external signal.

D1
PR
Q1 D2 Q2 D3 Q3 D Q4

1 2 3 4

Q1’ Q2’ Q3’ Q4’

R R R R

CLK
CLEAR
JOHNSON COUNTER/TWISTED RING COUNTER
State Diagram Reduction for the 0/0
Input sequence a
01010110100
1/0 0/0 0/0
0/0 b 0/0 c

1/0 0/0 e

g d
1/1
1/1 1/1
0/0
f
1/1
1. Form the sequence table.
2. Form the state table.
3. Identify the equivalent states(if two states have the same next state and same
output for the given input).
4. Remove one of the same state.(last state)
5. Replace the removed state by considered state in the state table.
6. Repeat step3,4,5 until there is no equivalent states.
7. Draw the new state table and reduced diagram.
Sequence Table
state a a b c d e f f g f g a
Input 0 1 0 1 0 1 1 0 1 0 0
Output 0 0 0 0 0 1 1 0 1 0 0

State Table
Present Next state Output
state X=0 X=1 X=0 X=1

a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g e f 0 1
g a f 0 1
Present Next state Output
state X=0 X=1 X=0 X=1

a a b 0 0
b c d 0 0
c a d 0 0
d e f d 0 1
e a f d 0 1
f e f 0 1
Reduced State Table

Present Next state Output

state X=0 X=1 X=0 X=1

a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
Reduced State Diagram 0/0
a
0/0
0/0
1/0
e b 0/0 c
1/1 1/0
1/0
0/0
d

1/1
Sequence detector
Draw a state diagram which will detect 3 consecutive ones (1s)

0
0
S0/0 S1/0
1

0 0 1

1
S3/1 S2/0

1
Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0
Map for JA

B’C’ B’C BC BC’

A’ 0 1 3 2

A 4 5 7 6
Map for JA

B’C’ B’C BC BC’

A’ 0 1 3 2

A 4 5 7 6
PISO- Parallel In serial Out shift register.