PRESIDENCY UNIVERISTY, BENGALURU

School of Engineering

Microprocessors and Microcontroller

CSE 206

IV Semester 2018-19
 Evaluation Components

Duration Weightage Marks Date &

Component Venue
(minutes) (%) (200M) Time

Continuous
NA 30 60
Evaluation
Quiz +
Assignment NA 20 40

End Term
Examination 120 50 100
Books
 Prescribed Text Books
 Microprocessors and Interfacing (SIE), 3rd ed. by Douglas
V. Hall & S.S.S.P. Rao, 3rd edition, Mc Graw Hill, 2012
 Barry
B Brey, “The Intel Microprocessors”, 8 th edition,
Pearson , 2014.
 Reference Book
 Muhammad Ali Mazidi, “Microprocessors and
Microcontrollers”, First Impression, Pearson Education.
Module-1
 Introduction
 Organization of Computer Systems
 Architecture of Computers
 RISC and CISC
 Microprocessor Evolution
 Main Features of 8086
 8086 Pin Diagram/Description
 8086 Internal Architecture
Introduction

 Computer Definition
 Hardware
 Passive Components
 Active Components
 Software
 1.1 Organization of Computer Systems
 Components of a Computer Device
 Central Processing Unit
 Main Memory
 Secondary Memory Main Memory Device
 I/O interfaces Controller
I/O
 Devices Interface
Device
CPU Controller

Byte/Bytes Char, Byte

(Memory access width) ASCII-7 Devic
ASCII-8 e
EBCDIC
Organization of Computer Systems Contd…..
 Input
is converted into standard 7 or 8 binary coded
characters and send to CPU
 CPU then send this information to main memory
 Bothdata and program are stored in main memory and
performs the specified operations on the data
 BUS is used to connect the components
 Unidirectional

 Bidirectional
1.2 Architecture of Computers
 Definition of architecture
2 types of architecture
 Von Neumann architecture
 Harvard architecture
Von Neumann architecture
 John Von Neumann suggested that, data &
programs should be stored together in
memory. This is now called Von Neumann
architecture.
 Hence this process being known as stored
program concept
 Uses single memory space for program and
data
 Limits operating bandwidth
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Von Neumann architecture Contd…..
 Now the question is how it differentiate data and information?
 When information is fetched from the main memory location
address through a Program Counter(PC) register, then that
information is a machine instruction
 If the information is fetched with the address specified from any
other register, then that information is a data
 Drawback of Von Neumann architecture
 Channel bandwidth is finite
 Processor can go no faster when this channel bandwidth is full
 This performance limiting factor is called Von Neumann bottleneck
 Harvard architecture
 It has 2 memories-----one for
architecture & the other for data
 Uses two separate memory spaces
for program instructions and data
 Improved operating bandwidth
 Allows for different bus widths
 Increased bandwidth available due
to separate buses for instructions &
data
 Disadvantage---storage is allocated
to instructions & data in a fixed ratio
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RISC and CISC
 Complex Instruction Set Computer(CISC)
 Developed by Intel
 Main idea is to minimize number of instructions per program,
sacrificing number of cycles per instruction
 Computers based on CISC are designed to decrease the memory
cost
 Largeprograms need more storage, as memory size increases it
becomes expensive
 To solve these problems, number of instructions per program can
be reduced by embedding the number of operations in a single
instruction, thereby making the instructions more complex
Reduced Instruction Set Computer (RISC)
 RISCarchitecture is used in portable devices due to its
power efficiency (Apple iPod)
 Uses highly optimized set of instructions
 Itreduces the cycles per instruction at the cost of the
number of instructions per program
 Pipelining is the unique feature of RISC
 Pipelining is performed by overlapping the execution of
several instructions in a pipeline fashion
Difference between RISC and CISC

CISC RISC
  Control unit is hardwired only
Control Unit is hardwired &
microprogrammed  Simple single clock instructions
 Complex multi clock instruction  Register reference instructions (except
 Memory reference instructions LOAD and STORE)
  More registers in CPU
Less registers in CPU
  Minimum memory addressing modes
Maximum memory addressing modes
  Large code sizes
Small code sizes
  Fixed instruction length
Variable instruction length
Microprocessor Evolution
 Microprocessor is a CPU on a single chip, consists of millions of transistors &
other electronic components that process millions of instructions per second
 Microprocessor is a versatile chip, that is combined with memory & special
purpose chips & preprogrammed by a software
 It accepts a digital data as input & process it according to the instructions
stored in the memory
 1971
 First microprocessor, intel 4004 which is a 4 bit bus
 Speed was 60000 operations per second
 2300 transistors based on 10-micron technology
 It can address 640 bytes
 It operates at 750 kHz
Contd……
 1972
 Intel introduces first 8 bit microprocessor intel 8008
 It can address 16K bytes of memory
 3500 transistors were used based on 10 micron technology
 Speed was 60000 operations per second
 1974
 intel released its 2MHz 8080 chip, an 8 bity microprocessor
 It can address 64K bytes of memory
 6000 transistors were used based on 6 micron technology
 Speed was 0.64 MIPS
Contd……
 1978
 Intel introduced 4.77 M Hz 8086 microprocessor.
 It has 16 bit registers, 16 bit data bus
 29000 transistors were used based on 3 micron technology
 It can address 1 M bytes of memory
 1979
 Intel introduced 4.77 M Hz 8088 microprocessor.
 It operates on 16 bits internally, but supports 8 bit data bits to
use existing 8 bit devices
 29000 transistors were used based on 3 micron technology
 It can address 1 M bytes of memory
 Its speed is 0.33 M Hz
Contd………
 1985
 Intel introduced 6 M Hz 80286 microprocessor
 134000 transistors were used based on 1.5 micron technology
 Offers protected mode operation
 It can address 16 M bytes of memory or 1 GB of Virtual memory
 Its speed is 0.9 M Hz
 1989
 Intel announced 25 M Hz486 microprocessor
 It integrated the 386, 387 math coprocessor & added an 8 KB primary cache
 It used 1.2 million transistors based on 1 micron technology
 Its speed is 20 MIPS
Contd…..
 1991
 Intel introduced 50 MHz 486 microprocessor.
 Speed is 41 MIPS
 1992
 Intel introduced 486 SL processor designed for notebook computers.
 Speed is 20 MHz. It can address 64MB of physical memory
 1.4 million transistors were used based on 0.8 micron technology
 1993
 Intel introduced Pentium processor & used 32 bit registers with a 64 bit data bus
 It can address 4GB of memory. Its speed was 60 MHz
 3.1million transistors were used based on 0.8 micron technology
Contd…….
 1994
 Intel introduced 75 MHz Pentium processor. Speed was 126.5 MIPS.
 It uses 3.2 million transistors based on 0.6 micron technology
 1995
 Intel released Pentium pro which contained 5.5 million transistors
 1996
 Intel released 150 MHz mobile pentium processor designed for use in
portable computers
 1997
 Intel released 7.7 million transistor Pentium II processor
Contd…….
 1999
 Intel released 450 MHz Pentium III processor. Its speed was 450 to 1.15 GHz
frequency
 2000
 Intel released Pentium IV operating at 2GHz
 2005
 Intel released its first desktop dual core processor called Pentium D
 291 million transistors were used at 3.2 GHz initial speed.
 Present status
 Intel stops Pentium series and started Intel Core i3 series from 2012.
 As of June 2018, the lineup of core processors included the Intel Core i9, Intel
Core i7, Intel Core i5 and Intel Core i3.
 Chapter 2

8086 Microprocessor Architecture

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Main Features of 8086
 16 bit processor
 16 bit data bus
 20 bit address bus
 Frequency range is 6-10 MHz
 Can do only fixed point arithmetic operations
 Along with coprocessor 8087, 8086 can do both fixed and floating
point operations
 It can operate in 2 modes
 Minimum

 maximum
Main Features of 8086 Contd….
 It works in multiprocessor environment, control signals for
memory & I/O are generated by an external BUS controller
 It can pre-fetch up to 6 instructions from memory & queues them
in order to speed up the execution
 It requires +5V power supply
 It uses a 40 pin dual in line package
 8086 has 2 blocks
 Bus Interfacing Unit (BIU)
 Execution Unit (EU)
8086 pin diagram/description
 Clock signal is given to pin 19. It
provides timing to the processor for
opertions. Its frequency is different
for different versions, i.e., 5MHz,
8MHz anmd 10 MHz
 AD0-AD15 are the 16 address/data
bus. These are multiplexed memory
or I/O address and data bus
 A16-A19/S3-S6 are the 4
address/status bus
 BHE is used to indicate the transfer
of data using data bus D8-D15
8086 pin diagram contd…….
 BHE is used to indicate the transfer of data using data bus D8-D15
 Ready is an acknowledgement signal from I/O devices that data is transferred
 RESET is used to restart the execution
 INTR is generated by I/O devices to inform processor that device is ready for data transfer
 INTA is generated by CPU on receiving INTR from I/O device
 ALE
 As address and data lines are multiplexed, at a time, either address or data will be
allowed to transfer through it.
 When ALE=1, acts as address bus
 When ALE=0, acts as data bus
 NMI
 When the processor does not want to ignore any I/O device, then it makes NMI of that
device as HIGH
 8086 Internal
Architecture
Execution Unit
EU Executes Instructions
that have already been
fetched by the BIU.
BIU and EU functions
separately

Bus Interface Unit

BIU Fetches Instructions, Reads data
from Memory and I/O Ports, Writes
data to Memory and I/O Ports
8086 Internal Architecture Contd…..
 8086 architecture is divided into 2 independent functional units
 Bus Interface Unit (BIU)
 Execution Unit (EU)

 Operations performed by BIU are  Operations performed by EU are

 Sending addresses  Informs BIU, where to fetch
 Fetches instructions from the instructions from
memory  Informs BIU. Where to fetch data
 Reads data from ports and from
memory  Decodes instructions
 Writes data to ports and memory  Executes the instructions
Execution Unit
 Control circuitry which directs & controls the internal operations
 Decoder which translates instructions fetched from memory into a series of
actions which the EU carries out
 16 bit ALU which can add, subtract, AND, OR, XOR, increment, decrement,
compliment & shift the binary numbers
 Flag Register
 6 conditional flags  3 control flags
 Carry flag  Zero flag  Trap flag
 Auxiliary flag  Sign flag  Interrupt flag
 Parity flag  Overflow flag  Direction flag
Execution Unit Contd……
 General Purpose Registers
 AH, AL (AX), BH, BL (BX), CH, CL (CX), DH, DL (DX)
 AX register ( accumulator) used to store operands for
arithmetic operations
 BX register is used as base register to store the starting base
address of memory area within the data segment
 CX register is used as counter in loop instructions
 DX register is used to hold I/O port address for I/O instruction
Bus Interface Unit
 Instruction Queue
 BIU fetches up to 6 instruction & stores them in the instruction queue
 Fetching the next instruction while the current instruction executes is
called pipelining
 Segment Registers
 At any time, 8086 works with only 4, 65536(64KB) segments within
1M byte range
 The 4 segment registers are
 Code segment  Extra segment
 Stack segment  Data segment
Bus Interface Unit Contd….
Bus Interface Unit Contd…..
 Instruction Pointer is a 16 bit register to hold the address of the next
instruction to be executed memory
 The value contained in the IP is Physical
referred to as an offset. This value address
must be offset from the segment
base address in CS to produce the
4489F H Top of CS
required 20 bit physical address

CS = 3 4 8 A 0 38AB4 H Code Byte

IP = 4 2 1 4

Physical address= 3 8 A B 4 348A0 H Start of CS

Bus Interface Unit Contd…..
 Stack Pointer is a 16 bit register to hold the 16 bit offset from the start of the
segment to the memory location where a word was most recently stored on the
stack Physical memory
 The memory location where a word address
was most recently stored is called as
top of stack
 Physical address for a stack read 5FFFF H End of SS
or stack write is produced by
adding the contents of SP to the 5FFE0 H Top of stack
segment base address
represented by the upper 16 bits
of the base address inSS
SS= 5 0 0 0 0
SP = F F E 0 50000 H Start of SS

Physical address= 5 F F E 0
Pointer & Index Registers in the EU
 EU contains another 3 registers, Base Pointer (BP), Source Index (SI) and
Destination Index (DI) registers.
 These are 16 bit registers used for temporary storage of data just like general
purpose registers
 SI is used to hold the offset of a data word in the data segment. Physical
address of the data in memory will be generated by adding contents of SI to
segment base address represented by 16 bit number in DS register
 DI can be used for pointer addressing of data & also used as destination in
some string processing instructions. Its offset address is relative to ES
 BP is used to access parameters passed via the stack. Its offset address is
relative to SS