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Dvlsi PD

This paper presents a novel capacitorless 3T-1D DRAM architecture aimed at reducing power dissipation and improving performance in digital VLSI design. It highlights the advantages of this design over traditional 1T-1C DRAM, including better scalability and lower leakage current. The findings suggest that 3T-1D DRAM cells can effectively address challenges in on-chip memory design as technology scales down.

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23 views17 pages

Dvlsi PD

This paper presents a novel capacitorless 3T-1D DRAM architecture aimed at reducing power dissipation and improving performance in digital VLSI design. It highlights the advantages of this design over traditional 1T-1C DRAM, including better scalability and lower leakage current. The findings suggest that 3T-1D DRAM cells can effectively address challenges in on-chip memory design as technology scales down.

Uploaded by

pooja
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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A Review On

Analysis of Power Dissipation in


Design of Capacitorless Embedded DRAM

for the subject


DIGITAL VLSI DESIGN
ABSTRACT
• This paper presents a new DRAM architecture for scaled
DRAMs.
• Recently the semiconductor industry tends to design a smaller
volume device and system with lower power consumption,
lower leakage current, and high speed performance.
• Semiconductor memory arrays capable of storing large
quantities of digital information are essential to all digital
system.
• This paper analyse effect on power dissipation of 3T-1D DRAM
by variation in voltage.
• Day by day DRAM is more used as compare to SRAM because
of cell area decreases as number of transistor decreases from
SRAM to DRAM design.
INTRODUCTION
• DRAM is used for storage of data.
• Traditional DRAM cell consists of one transistor and one capacitor.
• Memory cell area is scalable by reducing its capacitor area, such as
using stacked capacitor, trench capacitor or high dielectric
constant materials etc.
• Therefore DRAM manufacturers faces challenge on shrinking the
memory cell area as the technology feature size need to be shrink
greatly.
• Recently new approach has been proposed for scaling down the
DRAM cell.
PLACEMENT OF CELL
DRAM DESIGN TREND

• As trend for high density memories favors small memory cell sizes
• DRAM cell with a small structure has become a popular choice,
where binary data are stored as a charge in a capacitor and the
presence or absence of stored charge determines the value of the
stored bit.
• The stored electrical charge will gradually leak away and the value
stored in the capacitor will no longer be resolvable after some time.
• Scaling of the conventional 1Transistor-1Capacitor (1T-1C) DRAM is
becoming increasingly difficult.
• Due to the capacitor which is harder to scale as device geometries
shrink.
• Recently the capacitorless (gated diode) three transistor-one diode
(3T-1D) DRAMs have attracted attention.
• Due to its ability to achieve higher memory cell density and to solve
the problems associated with the scaling of the capacitor.
• The information is stored as different charge levels at a capacitor in
conventional 1T-1C DRAM, whereas the 3T-1D DRAM employs voltage
controlled capacitor within the transistor to store the information
without the need of the capacitor.
• Due to the threshold voltage of T1, there is a degraded level on the
storage node when storing a “1”.
• Hence, it relies on a “gated diode” (D) to improve array access speed. This
diode can be thought of as being a voltage controlled capacitor
• with larger capacitance when storing a “1” and a smaller capacitance
when storing a “0.”
• Each time the cell is read, the bottom side of this capacitor is also raised
to VDD.
• If the cell stores a “1” and it is read, the charge stored on the big capacitor
of D1 boosts up the turn-on voltage of T2, rapidly discharging the bitline.
• As a result, the access speed can match the speed of 6T SRAM cells.
ADVANTAGES OF GATED DIODE DRAM

• The absence of the capacitor is advantageous in terms of


• scalability
• process and fabrication complexity
• compatibility with the logic processing steps
• device density, yield and cost.
• Due to all these advantages of the capacitorless(gated diode) DRAM,
solve the scaling problem of conventional 1T-1C DRAM, this work is
focused on creating novel single transistor DRAM technologies.
PERFORMANCE
ANALYSIS
• Simulations is performed using Tanner EDA tool using two
methods.
1) Voltage constant at 4V
2) Technology constant 0.18 μm

• The main purpose of Technology variation is to determine the


efficiency, power dissipation and leakage current of 3T-1D DRAM
Cells.
1) Voltage constant at 4V
• When applying voltage is kept constant i.e. 4V
• Technology changes from 0.18 μm to 1 μm for 3T-1D DRAM architecture
then we get different leakage current for different technology.
• The leakage current and power dissipation for different technology is
shown below
2. Technology constant 0.18 μm
• When technology is kept constant i.e. 0.18 μm
• applying voltages changes from 5V, 4V, 3V, 2.5V and 1.8V for same 3T- 1D DRAM
architecture then we get different power dissipation for different voltages.
• The leakage current and power dissipation for different technology is shown
below.
CONCLUSION

• 3T-1D DRAM cell is an attractive alternative to conventional 6T cells for next-


generation on-chip memory designs since they offer better tolerance to process
variations that impact performance, cell stability, and leakage power.
• From the above results of power calculation of 3T-1D DRAM Cell of the different
technologies, it is observed that power consumption increases as length and
width of the transistor decreases. It is because when the aspect ratio of MOS
decreases the gate loses control over the current, hence the overall power
consumption increases.
• Also after simulating schematic design in tanner tool and layout it is observed that
digital technology gives less power dissipation as compared to analog technology.
• Further research can be carried to get high stability, reduce power requirement
and the ability to tolerate performance variation. This approach provides a
comprehensive solution to many of the issues that will impact on-chip memory
design in nano scale process technologies.
THANK
YOU

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