2021 International Conference on Computer Information Science and Artificial Intelligence (CISAI)

Elevator Control Chip Design

TianAi Yue
Tianjin Nankai High SchoolˈNo. 22, Nankai 4th Road, Nankai District, Tianjin, China
[email protected]

Abstract—With the rapid development of urbanization, high- an example, and intends to realize the following functions:
rise buildings and intelligent buildings will emerge in large
numbers. At the same time, the conditions for the continuous (1)The internal signals of the elevators on each
2021 International Conference on Computer Information Science and Artificial Intelligence (CISAI) | 978-1-6654-0692-5/21/$31.00 ©2021 IEEE | DOI:

improvement of elevator control systems are provided by the floor: request buttons for each floor, door opening and
rapid development of integrated circuit and fieldbus technology. closing request buttons, the floor display, and the elevator
As the modern elevator control system is constantly improving in running status display. External signal: ascending and
terms of safety, stability, and humanization, it is particularly descending request button, the floor display, the elevator
necessary to upgrade the original system in terms of running status display.
communication and motor control methods. At present, elevator
control mainly includes several control methods such as relay (2)The signal request can be stored. During the
control, single- chip control, PLC control and FPGA/CPLD elevator's ascending (descending) process, according to the
control. This article uses FPGA as the control method, which is a elevator's running status, the direction is first given priority,
high-density application specific integrated circuit that can be and the cyclic order corresponds to each request. When the
customized and configured by the user. The FPGA-based elevator starts to run after stopping, first consider whether
elevator control method has the advantages of high reliability, there is a request in the running direction, and continue to run
convenient maintenance, short development cycle, and strong if there is a request, and then consider whether there is a
flexibility. It can complete complex control tasks and has become request in the opposite direction, and then turn to run, if there
the development direction of elevator control. is no request, the elevator stops at the current floor and is
This article takes the three-story elevator control system as waiting status.
an example, and uses Verilog to design a set of control
chip design, including button request module, state control (3)After arriving at the requested floor, the indicator
module, motor drive module, switch door control module, and of the floor lights up, the elevator door opens automatically,
frequency divider module. Finally, the FPGA development and the door open status is displayed at the same time.
platform was used for implementation and verification. After hiding and waiting, the elevator door closes
automatically (door opening display stops), and the
Keyword˖elevator control, intelligent buildings, FPGA elevator runs automatically.

I. Introduction III. Design method

An integrated circuit is a miniature electronic device or The development software of this design uses Altera's
component. A certain process is used to interconnect the Quart us " integrated development environment [1], adopts a
transistors, resistors, capacitors, inductors and other top-down design method [2], and the input method that
components and wiring required in a circuit, fabricate on a combines module design and Verilog HDL description [3],
small or several small semiconductor wafers or dielectric which is convenient for program maintenance And upgrade.
substrates, and then package them in a package[6]. It has As shown in Figure 1, FPGA control programming is mainly
become a miniature structure with the required circuit composed of five modules: key request module, status control
functions - all components have been structured as a whole, module, motor drive module, switch gate control module, and
and electronic components are progressing towards frequency division module. The signals and functions of each
miniaturization, low power consumption, intelligence and module are as follows:
high reliability[7]. Integrated circuit technology includes chip
Module 1: Button request module
manufacturing technology and design technology, mainly
embodied in processing equipment, processing technology, The function of this module is as follows:
10.1109/CISAI54367.2021.00144

packaging and testing, mass production and design innovation

capabilities[9]. Integrated circuits have the advantages of (4)Use the latch to store the input request signal and
small size, light weight, few lead wires and soldering points, clear it to 0 when the request is satisfied. For the
long life, high reliability, and good performance[8]. At the convenience of data presentation, the suffixes 0 ̚ 3 of
same time, they have low cost and are convenient for mass this design respectively represent the 1st to 3rd layers.
production. It is not only widely used in industrial and civilian (5)According to the running status of the elevator and
electronic equipment such as tape recorders, televisions, the principle of direction priority and circular execution, the
computers, etc., but also in military, communications, and floor signal of the next station of the elevator is extracted
remote control[10]. and output from the request signal. If the current floor is 2 and
II. Design objects the status is ascending, then the judgment priority is:
Sl2/Up2- 3→Sl3/Down3-2→Down2- 1→Sl1/Up1-2.
This article takes the three-story elevator control system as
(6) When there is no request signal, the next station floor is

978-1-6654-0692-5/21/$31.00 ©2021 712

IEEE DOI
10.1109/CISAI54367.2021.00144
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 0. controller, which is output to the motor drive circuit. Its
frequency determines the motor rotation, and its phase
Module 2: State control module
determines the motor rotation direction L[ 3: 0] Each
This module is the core control module of the system frequency signal of is provided by the frequency divider
design. It mainly judges and responds to external input signals module.
to control various actions of the elevator. Through the Module 4: Switch gate control module
asynchronous reset signal, the system can be reset
immediately, which can ensure that the system in the fault This module is used to control the status of the elevator
state can resume normal operation in the shortest time. After door. The door is opened by the input door control signal
processing, some control signals must be sent to the display (open = 1). After a delay, the elevator door is automatically
control module for the latter to display and output. An closed (close = 0).
important function of the main control module is to judge the
call request of the guests, and transport the passengers to the Module 5: Frequency division module
designated building according to certain rules. The frequency division module is used to divide the
Floor. The elevator operation rule adopts the same frequency of the system clock signal to generate various
direction priority principle, that is, the call elevator request in frequency signals provided to the motor control module.
the same direction as the elevator operation is executed first. IV. Experimental results and analysis
This article divides the elevator operation into 5 states, A. Experimental setup
namely: ascending, descending, stopping, door opening, and
door closing. The state transition diagram of the control This experiment was carried out in Verilog HDL. The
system is shown in Figure 1. Verilog HDL language is one of the IEEE standard hardware
description languages. Its grammatical structure is free, easy
to master, and flexible in design. Therefore, the Verilog HDL
language has become one of the most commonly used tools
for FPGA programming [4]. Because of its flexible design,
different programming styles make the performance of the
designed circuit very different. The following article will
specifically introduce how to write different styles of Verilog
HDL programs for the same circuit based on pipeline design
and resource sharing design ideas to achieve the purpose of
improving circuit performance.
B. Design code
Figure 1. The state transition diagram of the control system Part of the program code of the sub-controller module is
shown in Code 1.
When the system restarts (res = 1), it enters the idle state
(Idle). In the idle state, the output signal Sl = up = down = module elavator(
open = close = 0. When the input signal is 0, it remains in the input rest,
idle state; when the signal is not 0. When it enters the rising input clock,
state (Stop). When the rising signal of the first layer is input [3:0] lamp,
triggered, it enters the stop state. In the stop state, the rising output [3:0] state
edge of the open signal triggers the elevator to open the door; );
up = down = 0, L = Sl. During the elevator door open delay
period (open = 1), the stop state is maintained; when the reg [3:0] reg_state;
elevator door is closed (dooropen = 0), the next station floor is
judged, if it is greater than the current floor, it enters the
ascending state, if it is less than the current floor, it enters the always @(posedge clock)
descending state . In the rising state, up = 1, updown = 01, L = begin
Sl, the motor control module is triggered to drag the motor up. if (rest==1)
The floor reached signal makes the system enter the stop state. reg_state<=0;
The same goes for the falling state. else if (reg_state==4'b0000)
begin
Module 3: Motor drive module if (lamp==4'b0001||
The input signals of this module are: rising trigger signal lamp==4'b0011)
(UP), falling trigger signal (DN), the floor (L) and the next reg_state<=4'b0111;
station floor (SL), else if (lamp==4'b0111||lamp==4'b1011)
reg_state<=4'b1101;
Output signal: 4 motor drive signals with different phases.
else if (lamp==4'b1001||lamp==4'b1000||
The module is triggered by the lift signal and generates 4
lamp==4'b1100)
phases of motor drive signal L[ 3: 0] through the motor state
reg_state<=4'b0111;
end

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 else if (reg_state==4'b0001) reg_state<=4'b0001;
begin end
if (lamp==4'b0000) else if (reg_state==4'b1011)
reg_state<=4'b1001; begin
else if (lamp==4'b0011||lamp==4'b1100) if (lamp==4'b0000||lamp==4'b1011)
reg_state<=4'b1111; reg_state<=4'b1001;
else if else if (lamp==4'b0011||
(lamp==4'b0111||lamp==4'b1001||lamp==4'b1000) lamp==4'b1100)
reg_state<=4'b1100; reg_state<=4'b1111;
else if (lamp==4'b1111) else if (lamp==4'b0111||lamp==4'b1111)
reg_state<=4'b0001; reg_state<=4'b1011;
else if (lamp==4'b1011) else if (lamp==4'b1001||lamp==4'b1000)
reg_state<=4'b1001; reg_state<=4'b0001;
end end
else if (reg_state==4'b0011) begin else if (reg_state==4'b1001)
if (lamp==4'b0000||lamp==4'b0001) begin
reg_state<=4'b1011; if
else if (lamp==4'b0111) (lamp==4'b0001||lamp==4'b0011||lamp==4'b1001||lamp==
reg_state<=4'b1000; 4'b1000||lamp==4'b1100)
else if reg_state<=4'b0111;
(lamp==4'b1011||lamp==4'b1001||lamp==4'b1000) else if (lamp==4'b0111||lamp==4'b1111)
reg_state<=4'b1011; reg_state<=4'b1001;
else if (lamp==4'b1100) else if (lamp==4'b1011)
reg_state<=4'b1000; reg_state<=4'b0000;
end end
else if (reg_state==4'b0111) else if (reg_state==4'b1101)
begin begin
if (lamp==4'b0000||lamp==4'b1011) if
reg_state<=4'b1001; (lamp==4'b0000||lamp==4'b0001||lamp==4'b0011||la
else if (lamp==4'b0011||lamp==4'b1100) mp==4'b0111||lamp==4'b1011||lamp==4'b1001||lamp
reg_state<=4'b1111; ==4'b1000||lamp==4'b1100)
else if (lamp==4'b1111) reg_state<=4'b1101;
reg_state<=4'b0111; else if (lamp==4'b1111)
else if (lamp==4'b1000||lamp==4'b1001) reg_state<=4'b1010;
reg_state<=4'b0001; end
end else if
else if (reg_state==4'b1111) (reg_state==4'b1100) begin
begin if (lamp==4'b0000||lamp==4'b0001||
if (lamp==4'b0000||lamp==4'b0001) lamp==4'b0011||la
reg_state<=4'b1011; mp==4'b0111||lamp==4'b1011||
else if (lamp==4'b0111) lamp==4'b1001||lamp
reg_state<=4'b1111; ==4'b1000||lamp==4'b1100)
else if (lamp==4'b1011|| reg_state<=4'b1100;
lamp==4'b1000) else if (lamp==4'b1111)
reg_state<=4'b1001; reg_state<=4'b0010;
else if (lamp==4'b1100) end
reg_state<=4'b0011; else if
end (reg_state==4'b1000) begin
else if (reg_state==4'b1011) if (lamp==4'b0000||lamp==4'b0001||
begin lamp==4'b0011||la mp==4'b0111||lamp==4'b1011||
if (lamp==4'b0000||lamp==4'b1011) lamp==4'b1001||lamp
reg_state<=4'b1001; ==4'b1000||lamp==4'b1100)
else if (lamp==4'b0011|| reg_state<=4'b1000;
lamp==4'b1100) else if (lamp==4'b1111)
reg_state<=4'b1111; reg_state<=4'b0110;
else if (lamp==4'b0111||lamp==4'b1111) end
reg_state<=4'b1011; else if
else if (lamp==4'b1001||lamp==4'b1000) (reg_state==4'b1010) begin

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 if (lamp==4'b0000||lamp==4'b0001|| #0 clock=0;
lamp==4'b0011||la mp==4'b1111||lamp==4'b1001|| #50 rest=0;
lamp==4'b1000||lamp #50 rest=1;
==4'b1100) #50 rest=0;
reg_state<=4'b0110; #50 lamp=0001;
else if (lamp==4'b0111||lamp==4'b1011) #50 lamp=0011;
reg_state<=4'b1101; #50 lamp=0111;
end #50 lamp=1111;
else if (reg_state==4'b0010) #50 lamp=1011;
begin #50 lamp=1001;
if (lamp==4'b0000||lamp==4'b0001|| #50 lamp=1000;
lamp==4'b0011||la #50 lamp=1100;
mp==4'b1111||lamp==4'b1011||lamp==4'b1100) #50 lamp=0001;
reg_state<=4'b0010; #50 lamp=0011;
else if end
(lamp==4'b0111||lamp==4'b1001||lamp==4'b1000)
reg_state<=4'b0110||4'b0010; endmodule
end Code 2
else if (reg_state==4'b0110)
C. Simulation results and analysis
begin
if (lamp==4'b0000||lamp==4'b0001|| Give a simulation waveform diagram and explain the
lamp==4'b0011||la mp==4'b1111||lamp==4'b1011|| meaning of this diagram
lamp==4'b1001||lamp The top layer of this design adopts modular design, and
==4'b1000) each module adopts Verilog HDL hardware description
reg_state<=4'b0110; language. The top-down design is convenient for program
else if (lamp==4'b0111) error checking, upgrading and improvement. With a slight
reg_state<=4'b1000; modification of this design, elevator control on any floor can
else if (lamp==4'b1100) be realized. After analyzing, compiling, synthesizing, and
reg_state<=4'b0110; wiring the designed program, the circuit produced by
end functional simulation and timing simulation can obtain logic
en values that meet the design requirements. The simulation
d result is shown in Figure 2.
assign state=reg_state;

endmodule
Code 1

The testbench is shown in Code 2.

module testbench(

);
reg clock;
always #100 clock=~clock; Figure 2. The simulation result

reg rest; It can be seen from Figure 3 that the controller can always
reg [3:0] lamp; effectively store the request signal of each floor, and can
wire [3:0] state; execute the request of each floor according to the direction
elavator priority and the cyclic order. The state of each signal meets the
inst_elavator( rest, design requirements. The program is pin- locked and
clock, downloaded to the device by programming. After testing, the
logic is completely correct and meets the design requirements.
lamp,
state V. Conclusion
);
The FPGA-based digital circuit design method has obvious
advantages in reliability, size, and cost, and has become one of
initial begin the main means to realize digital circuits. The three-story

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 elevator controller designed in this paper sets the number of
floors in the signal acquisition module and the main control
module in the form of parameter configuration. It can be
applied to any floor with a slight improvement. It has good
scalability, strong flexibility, reliable operation, and is very
practical.
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