EEE-

3209
Microprocessor, Interfacing and
System design

Prof. Dr. Md. Shahidul Islam

Contact: 01750 194739

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February 2, 2025 North Bengal International University 5
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Memory

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Example Microprocessor System

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 Microprocessor Fifth Generation Pentium

Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology  Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 11
multiplexed Intel 8085 (8 bit processor)
 Microprocessor Functional blocks

Various conditions of the

Computational Unit;
results are stored as
performs arithmetic and Internal storage of data
status bits called flags in
logic operations
flag register

Register array or Data Bus

internal memory
ALU
Generates the
Instruction address of the
Flag decoding unit instructions to be
Register fetched from the
memory and send
through address
bus to the
Timing and memory
control unit PC/ IP

Control Bus Address Bus

Generates control signals for

internal and external Decodes instructions; sends
operations of the information to the timing and
control unit 12
microprocessor
 8086
Microprocessor
Overview

First 16- bit processor released by

INTEL in the year 1978

Originally HMOS, now manufactured

using HMOS III technique

Approximately 29, 000 transistors, 40

pin DIP, 5V supply

Does not have internal clock; external

asymmetric clock source with 33% duty
cycle

20-bit address to access memory  can

address up to 220 = 1 megabytes of
memory space.

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Architecture

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 8086
Microprocessor
Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
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 8086
Architecture Bus Interface Unit (BIU)
Microprocessor

Dedicated Adder to
generate 20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >> 16

 8086
Architecture Bus Interface Unit (BIU)
Microprocessor

Segment
Registers

8086’s 1-megabyte The 8086 can directly Programs obtain access

memory is divided address four segments to code and data in the
into segments of up (256 K bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.

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 8086
Architecture Bus Interface Unit (BIU)
Microprocessor

Segment Code Segment Register

Registers
16-bit

CS contains the base or start of the current code segment;

IP contains the distance or offset from this address to the
next instruction byte to be fetched.

BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then adding
the 16-bit contents of IP.

That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then offset
is added provided by the IP.

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 8086
Architecture Bus Interface Unit (BIU)
Microprocessor

Segment Data Segment Register

Registers
16-bit

Points to the current data segment; operands for most

instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or Destination

Index (DI) or a 16-bit displacement are used as offset for
computing the 20-bit physical address.

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 8086
Architecture Bus Interface Unit (BIU)
Microprocessor

Segment Stack Segment Register

Registers
16-bit

Points to the current stack.

The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.

In based addressing mode, the 20-bit physical stack

address is calculated from the Stack segment (SS) and the
Base Pointer (BP).

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 8086
Architecture Bus Interface Unit (BIU)
Microprocessor

Segment Extra Segment Register

Registers
16-bit

Points to the extra segment in which data (in excess of 64K

pointed to by the DS) is stored.

String instructions use the ES and DI to determine the 20-

bit physical address for the destination.

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 8086
Architecture Bus Interface Unit (BIU)
Microprocessor

Segment Instruction Pointer

Registers
16-bit

Always points to the next instruction to be executed within

the currently executing code segment.

So, this register contains the 16-bit offset address pointing

to the next instruction code within the 64Kb of the code
segment area.

Its content is automatically incremented as the execution of

the next instruction takes place.

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 8086
Architecture Bus Interface Unit (BIU)
Microprocessor

Instruction queue

A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.

This is done in order to

speed up the execution
by overlapping
instruction fetch with
execution.

This mechanism is known

as pipelining.

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 8086
Architecture Execution Unit (EU)
Microprocessor

EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 24
DX can be used as DH and DL
 8086
Architecture Execution Unit (EU)
Microprocessor

EU Accumulator Register (AX)

Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word, and
AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or

AL.

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 8086
Architecture Execution Unit (EU)
Microprocessor

EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word, and

BH contains the high-order byte.

This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

All memory references utilizing this register content for

addressing use DS as the default segment register.

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 8086
Architecture Execution Unit (EU)
Microprocessor

EU Counter Register (CX)

Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

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 8086
Architecture Execution Unit (EU)
Microprocessor

EU
Registers

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 8086
Architecture Execution Unit (EU)
Microprocessor

EU Stack Pointer (SP) and Base Pointer (BP)

Registers
SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during

execution of instructions that involve the stack segment in
the external memory.

SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH instruction.

BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.

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 8086
Architecture Execution Unit (EU)
Microprocessor

EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

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 8086
Architecture Execution Unit (EU)
Microprocessor

EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

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 8086
Architecture Execution Unit (EU)
Microprocessor
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case of
subtraction. subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed
enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 32
 8086
Microprocessor
Architecture

8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF C
F

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

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 8086
Microprocessor
Architecture Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic

operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic

operations

BX Base register Used to hold base value in base addressing mode

to access memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE

and LOOP instructions

DX Data Register Used to hold data for multiplication and division

operations

SP Stack Pointer Used to hold the offset address of top stack

memory

BP Base Pointer Used to hold the base value in base addressing

using SS register to access data from stack
memory

SI Source Index Used to hold index value of source operand (data)

for string instructions

DI Data Index Used to hold the index value of destination

operand (data) for string operations 34
Pins and signals

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 8086
Microprocessor
Pins and Signals Common signals

AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals

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 8086
Microprocessor
Pins and Signals Common signals

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
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 8086
Microprocessor
Pins and Signals Common signals

READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.

The signal is active high. 38

 8086
Microprocessor
Pins and Signals Common signals

RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request
is pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

synchronized. 39
 8086
Microprocessor
Pins and Signals Min/ Max Pins

The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

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 8086
Microprocessor
Pins and Signals Minimum mode signals

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

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 8086
Microprocessor
Pins and Signals Minimum mode signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the
control of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

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 8086
Microprocessor
Pins and Signals Maximum mode signals

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 8086
Microprocessor
Pins and Signals Maximum mode signals

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 8086
Microprocessor
Pins and Signals Maximum mode signals

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ADDRESSING MODES
&
Instruction set

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 8086
Microprocessor
Introduction

Program
A set of instructions written to solve
a problem.

Instruction
Directions which a microprocessor
follows to execute a task or part of a
task.

Computer language

High Level Low Level

Machine Language Assembly Language

 Binary bits  English Alphabets

 ‘Mnemonics’
 Assembler
Mnemonics  Machine
Language 47
ADDRESSING MODES

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 8086
Microprocessor
Addressing Modes

Every instruction of a program has to operate on a data.

The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for
10. Indirect I/O port Addressing I/O ports

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing mode

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 8086 Group I : Addressing modes for
Microprocessor
Addressing Modes register and immediate data

1. Register Addressing The instruction will specify the name of the

register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL

7. Based Index Addressing (CL)  (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

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 8086 Group I : Addressing modes for
Microprocessor
Addressing Modes register and immediate data

1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL)  08H

8. String Addressing

9. Direct I/O port Addressing

MOV AX, 0A9FH

10. Indirect I/O port Addressing The 16-bit data (0A9FH) given in the instruction is
moved to AX register
11. Relative Addressing
(AX)  0A9FH
12. Implied Addressing

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 8086
Microprocessor
Addressing Modes : Memory Access

20 Address lines  8086 can address up to

220 = 1M bytes of memory

However, the largest register is only 16 bits

Physical Address will have to be calculated

Physical Address : Actual address of a byte in
memory. i.e. the value which goes out onto the
address bus.

Memory Address represented in the form –

Seg : Offset (Eg - 89AB:F012)

Each time the processor wants to access

memory, it takes the contents of a segment
register, shifts it one hexadecimal place to the
16 bytes of
left (same as multiplying by 16 10), then add the contiguous memory
required offset to form the 20- bit address

89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
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 8086 Group II : Addressing modes
Microprocessor
Addressing Modes for memory data

1. Register Addressing

2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.

5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
7. Based Index Addressing
MOV BX, [1354H]
8. String Addressing MOV BL, [0400H]
9. Direct I/O port Addressing
The square brackets around the 1354H denotes
10. Indirect I/O port Addressing the contents of the memory location. When
executed, this instruction will copy the contents
11. Relative Addressing of the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.

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 8086 Group II : Addressing modes
Microprocessor
Addressing Modes for memory data

1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.

3. Direct Addressing Registers used to hold EA are any of the following

registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
6. Indexed Addressing
address calculation.
7. Based Index Addressing
Example:
Note : Register/ memory
8. String Addressing enclosed in brackets refer
MOV CX, [BX]
to content of register/
9. Direct I/O port Addressing memory
Operations:
10. Indirect I/O port Addressing
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
12. Implied Addressing
(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA +1)
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 8086 Group II : Addressing modes
Microprocessor
Addressing Modes for memory data

1. Register Addressing In Based Addressing, BX or BP is used to hold the

base value for effective address and a signed 8-
2. Immediate Addressing bit or unsigned 16-bit displacement will be
specified in the instruction.
3. Direct Addressing
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.

5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
6. Indexed Addressing
When BP holds the base value of EA, BP and SS is
7. Based Index Addressing
used.
8. String Addressing
Example:
9. Direct I/O port Addressing
MOV AX, [BX + 08H]
10. Indirect I/O port Addressing
Operations:
11. Relative Addressing
0008H  08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA

(AX)  (MA) or,

(AL)  (MA) 58
(AH)  (MA + 1)
 8086 Group II : Addressing modes
Microprocessor
Addressing Modes for memory data

1. Register Addressing SI or DI register is used to hold an index value for

memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
3. Direct Addressing
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.

5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
6. Indexed Addressing

7. Based Index Addressing

Example:
8. String Addressing
MOV CX, [SI + 0A2H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing
FFA2H  A2H (Sign extended)
11. Relative Addressing
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
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 8086 Group II : Addressing modes
Microprocessor
Addressing Modes for memory data

1. Register Addressing In Based Index Addressing, the effective address

is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
6. Indexed Addressing
000AH  0AH (Sign extended)
7. Based Index Addressing

8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA
10. Indirect I/O port Addressing
(DX)  (MA) or,
11. Relative Addressing
(DL)  (MA)
12. Implied Addressing (DH)  (MA + 1)

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 8086 Group II : Addressing modes
Microprocessor
Addressing Modes for memory data

1. Register Addressing Employed in string operations to operate on

string data.
2. Immediate Addressing
The effective address (EA) of source data is
3. Direct Addressing stored in SI register and the EA of destination is
stored in DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES
6. Indexed Addressing

7. Based Index Addressing

Example: MOVS BYTE
8. String Addressing
Operations:
9. Direct I/O port Addressing
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA

11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
12. Implied Addressing

Note : Effective address of (MAE)  (MA)

the Extra segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI)  (SI) +1 and (DI) = (DI) +61 1
 8086 Group III : Addressing
Microprocessor
Addressing Modes modes for I/O ports

1. Register Addressing These addressing modes are used to access data

from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.

4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing Operations: PORTaddr = 09H

(AL)  (PORT)
6. Indexed Addressing

7. Based Index Addressing Content of port with address 09H is

moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.
11. Relative Addressing
Example: OUT [DX], AX
12. Implied Addressing
Operations: PORTaddr = (DX)
(PORT)  (AX)

Content of AX is moved to port

whose address is specified by DX
register. 62
 8086 Group IV : Relative
Microprocessor
Addressing Modes Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
6. Indexed Addressing
Operations:
7. Based Index Addressing

8. String Addressing 000AH  0AH (sign extend)

9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
11. Relative Addressing
MA = BA + EA
12. Implied Addressing
If ZF = 1, then the program control jumps to
new address calculated above.

If ZF = 0, then next instruction of the

program is executed.
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 8086 Group IV : Implied
Microprocessor
Addressing Modes Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

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INSTRUCTION SET

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 8086
Microprocessor
Instruction Set

8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

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 8086
Microprocessor
Instruction Set

1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.

Generally involve two operands: Source operand and

Destination operand of the same size.

Source: Register or a memory location or an immediate data

Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/ memory.

67
 8086
Microprocessor
Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, mem (reg2)  (mem)

MOV reg/ mem, data

MOV reg, data (reg)  data

MOV mem, data (mem)  data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)

68
 8086
Microprocessor
Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

PUSH reg16/ mem

PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)

PUSH mem (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 1610 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2

POP mem MA S = (SS) x 1610 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2 69
 8086
Microprocessor
Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)

IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX)

(AX)  (PORT) (PORT)  (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL)  (addr8) OUT addr8, AL (addr8)  (AL)

IN AX, addr8 (AX)  (addr8) OUT addr8, AX (addr8)  (AX)

70
 8086
Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADD reg2, reg1 (reg2)  (reg1) + (reg2)

ADD reg2, mem (reg2)  (reg2) + (mem)
ADD mem, reg1 (mem)  (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data

ADD A, data

ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16

71
 8086
Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF

ADC A, data

ADD AL, data8 (AL)  (AL) + data8+CF

ADD AX, data16 (AX)  (AX) +data16+CF

72
 8086
Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2)  (reg1) - (reg2)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data

SUB A, data

SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16

73
 8086
Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2)  (reg1) - (reg2) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF

SBB A, data

SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF

74
 8086
Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8)  (reg8) + 1

INC reg16 (reg16)  (reg16) + 1

INC mem (mem)  (mem) + 1

DEC reg/ mem

DEC reg8 (reg8)  (reg8) - 1

DEC reg16 (reg16)  (reg16) - 1

DEC mem (mem)  (mem) - 1

75
 8086
Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

MUL reg/ mem

MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

IMUL reg/ mem

IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

76
 8086
Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

DIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

77
 8086
Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

IDIV reg/ mem

IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

IDIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

78
 8086
Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags  (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags  (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags  (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

79
 8086
Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags  (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags  (mem) – (mem)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

80
 8086
Microprocessor
Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags  (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags  (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

81
 8086
Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

82
 8086
Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

83
 8086
Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

84
 8086
Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

85
 8086
Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

86
 8086
Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

87
 8086
Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

88
 8086
Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

89
 8086
Microprocessor
Instruction Set

4. String Manipulation Instructions

 String : Sequence of bytes or words

 8086 instruction set includes instruction for string movement, comparison,

scan, load and store.

 REP instruction prefix : used to repeat execution of string instructions

 String instructions end with S or SB or SW.

S represents string, SB string byte and SW string word.

 Offset or effective address of the source operand is stored in SI register

and that of the destination operand is stored in DI register.

 Depending on the status of DF, SI and DI registers are automatically

updated.

 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.

 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

90
 8086
Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

REP

REPZ/ REPE While CX  0 and ZF = 1, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) – 1
ZF = 0)

REPNZ/ REPNE While CX  0 and ZF = 0, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) - 1
ZF = 1)

91
 8086
Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE)  (MA)

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1

If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

MOVSW MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1)  (MA; MA + 1)

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2

If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2
92
 8086
Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Compare two string byte or string word

CMPS

CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

Modify flags  (MA) - (MAE)

If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
CMPSW
If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

For word operation

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2
If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2
93
 8086
Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
Scan (compare) a string byte or word with accumulator
SCAS

SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)

If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0

If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

SCASW
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)

If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0
94
If DF = 0, then (DI)  (DI) + 2
 8086
Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to AX

LODS

LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)

If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1

LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)

If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2

95
 8086
Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to string

STOS

STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

STOSW MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1 )  (AX)

If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2

96
 8086
Microprocessor
Instruction Set

5. Processor Control Instructions

Mnemonics Explanation
STC Set CF  1

CLC Clear CF  0

CMC Complement carry CF  CF/

STD Set direction flag DF  1

CLD Clear direction flag DF  0

STI Set interrupt enable flag IF  1

CLI Clear interrupt enable flag IF  0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a coprocessor

which shares the address and data bus
with the 8086

LOCK Lock bus during next instruction 97

 8086
Microprocessor
Instruction Set

6. Control Transfer Instructions

Transfer the control to a specific destination or target instruction

Do not affect flags

 8086 Unconditional transfers

Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

98
 8086
Microprocessor
Instruction Set

6. Control Transfer Instructions

 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions

Checks flags

If conditions are true, the program control is

transferred to the new memory location in the same
segment by modifying the content of IP

99
 8086
Microprocessor
Instruction Set

6. Control Transfer Instructions

 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions

Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0

JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or Jump if above Jump if not below
equal or equal
JGE disp8 JNL disp8 JAE disp8 JNB disp8
Jump if greater Jump if not less Jump if above or Jump if not below
than or equal equal
JL disp8 JNGE disp8 JB disp8 JNAE disp8
Jump if less than Jump if not Jump if below Jump if not above
greater than or or equal
equal
JLE disp8 JNG disp8 JBE disp8 JNA disp8
Jump if less than Jump if not Jump if below or Jump if not above
or equal greater equal 100
 8086
Microprocessor
Instruction Set

6. Control Transfer Instructions

 8086 conditional branch instructions affecting individual

flags
Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, Z = 1

JNZ disp8 Jump if result is not zero, i.e, Z = 1

101
Assembler directives

102
 8086
Microprocessor
Assemble Directives

Instructions to the Assembler regarding the program being

executed.

Control the generation of machine codes and organization of

the program; but no machine codes are generated for
assembler directives.

Also called ‘pseudo instructions’

Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..

103
 8086
Microprocessor
Assemble Directives

DB Define Byte

DW Define a byte type (8-bit) variable

SEGMENT Reserves specific amount of memory

ENDS locations to each variable

ASSUME Range : 00H – FFH for unsigned value;

00H – 7FH for positive value and
ORG
END 80H – FFH for negative value
EVEN
EQU General form : variable DB value/ values

PROC
FAR Example:
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for
SHORT the variable LIST and each data specified in the
instruction are stored as initial value in the reserved
MACRO memory location
ENDM 104
 8086
Microprocessor
Assemble Directives

DB Define Word

DW Define a word type (16-bit) variable

SEGMENT Reserves two consecutive memory locations

ENDS to each variable

ASSUME Range : 0000H – FFFFH for unsigned value;

0000H – 7FFFH for positive value
ORG
END and 8000H – FFFFH for negative value
EVEN
EQU General form : variable DW value/ values

PROC
FAR Example:
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for
SHORT the variable ALIST and each 16-bit data specified in
the instruction is stored in two consecutive memory
MACRO location.
ENDM 105
 8086
Microprocessor
Assemble Directives

DB SEGMENT : Used to indicate the beginning of

a code/ data/ stack segment
DW
ENDS : Used to indicate the end of a code/
SEGMENT data/ stack segment
ENDS
General form:
ASSUME

ORG
END Segnam SEGMENT
EVEN
…
EQU … Program code
… or
PROC … Data Defining Statements
…
FAR …
NEAR
ENDP Segnam ENDS

SHORT

MACRO User defined name of

the segment
ENDM 106
 8086
Microprocessor
Assemble Directives

DB Informs the assembler the name of the

program/ data segment that should be used
DW for a specific segment.

SEGMENT General form:

ENDS
ASSUME segreg : segnam, .. , segreg : segnam
ASSUME

ORG
User defined name of
END Segment Register
the segment
EVEN
EQU

PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the
ENDP instructions of the program are
stored in the segment ACODE and
data are stored in the segment
SHORT ADATA

MACRO
ENDM 107
 8086
Microprocessor
Assemble Directives

ORG (Origin) is used to assign the starting address

DB
(Effective address) for a program/ data segment

DW END is used to terminate a program; statements

after END will be ignored
SEGMENT
ENDS EVEN : Informs the assembler to store program/
data segment starting from an even address
ASSUME
EQU (Equate) is used to attach a value to a
variable
ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements
EQU following ORG 1000H should be stored in
memory starting with effective address
1000H
PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of
SHORT ORG 1200H memory location assigned to A will be 1200 H
A DB 4CH and that of B will be 1202H and 1203H.
EVEN
MACRO B DW 1052H
ENDM _SDATA ENDS 108
 8086
Microprocessor
Assemble Directives

PROC Indicates the beginning of a procedure

DB
ENDP End of procedure
DW
FAR Intersegment call
SEGMENT
ENDS NEAR Intrasegment call

General form
ASSUME

ORG
procname PROC[NEAR/ FAR]
END
EVEN …
… Program statements of the
EQU procedure
…

PROC RET Last statement of the

procedure
ENDP
FAR procname ENDP
NEAR

SHORT User defined name of

the procedure
MACRO
ENDM 109
 8086
Microprocessor
Assemble Directives

DB
Examples:
DW

SEGMENT ADD64 PROC NEAR The subroutine/ procedure named ADD64 is

ENDS declared as NEAR and so the assembler will
… code the CALL and RET instructions involved
… in this procedure as near call and return
ASSUME …

RET
ORG
ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT
is declared as FAR and so the assembler will
… code the CALL and RET instructions involved
PROC … in this procedure as far call and return
ENDP …
FAR
RET
NEAR CONVERT ENDP

SHORT

MACRO
ENDM 110
 8086
Microprocessor
Assemble Directives

DB Reserves one memory location for 8-bit

signed displacement in jump instructions
DW
Example:
SEGMENT
ENDS

ASSUME JMP SHORT The directive will reserve one

AHEAD memory location for 8-bit
ORG displacement named AHEAD
END
EVEN
EQU

PROC
ENDP
FAR
NEAR

SHORT

MACRO
ENDM 111
 8086
Microprocessor
Assemble Directives

DB MACRO Indicate the beginning of a macro

DW ENDM End of a macro

SEGMENT General form:

ENDS

ASSUME macroname MACRO[Arg1, Arg2 ...]

Program
… statements in
ORG … the macro
END …
EVEN
EQU macroname ENDM

PROC
ENDP
FAR User defined name of
NEAR the macro

SHORT

MACRO
ENDM 112
 8086
Microprocessor
8086 and 8088 comparison

8086 8088

Similar EU and Instruction set ; dissimilar BIU

16-bit Data bus lines obtained by 8-bit Data bus lines obtained by
demultiplexing AD0 – AD15 demultiplexing AD0 – AD7

Two banks of memory each of 512 Single memory bank

kb

6-bit instruction queue 4-bit instruction queue

Clock speeds: 5 / 8 / 10 MHz 5 / 8 MHz

113
114