Oda Bultum University

Institute of Technology
Department of Electrical and Computer Engineering
(communication Engineering)
5th year Second semester
Switching and Intelligent Networks
By: Ahmed A. (MSc)
 Chapter 3
Outline
Switching Systems
 Packet Switching
 Packet switch: Datagram networks & VC networks
 Blocking in packet switching
 Switch generations
 Switch fabrics and shared memory switches
 Case study: ATM

2
 Packet switching
 In a circuit switch, path of a sample is determined at time of connection
establishment
– No need for a sample header--position in frame is enough
 In a packet switch, packets carry a destination field
– Need to look up destination port on-the-fly
– Datagram
• lookup based on entire destination address
– Cell
• lookup based on VCI (virtual circuit identifier)
Packet Switching: OSI layer entities
• Repeaters: at physical level
• Bridges: at datalink level (based on MAC addresses) (L2)
– discover attached stations by listening
• Routers: at network level (L3)
– participate in routing protocols
• Application level gateways: at application level (L7)
– treat entire network as a single hop
– e.g mail gateways and transcoders
 Structure of a packet switch/router
Control

1 Line Card Line Card 1

2 Line Card Line Card 2

Interconnecti
3 Line Card Line Card 3

Fabric
on
…

…
…

…
N Line Card Line Card N

Components: input ports, output ports, interconnection fabric, controller

A line card handles several pairs of input/output ports and implements physical layer and data

link layer functions: symbol timing, line coding, framing, physical addressing, error checking,
MAC protocol, data link protocol, and buffering.
 Resources and bottlenecks in switches
• Processing, memory and bus bandwidth

– Processing implements protocols, hence processing capacity places a limit on maximum rate at which
switch can operate
– Memory stores packets, hence the amount of memory determines the rate at which packets are lost,
placing another limit on switch load, moreover memory bandwidth also place limit on switch rate
– I/O bus bandwidth places a limit on total rate at which information can be transferred between
ports.

 Three generations of packet switches

• Different trade-offs between cost and performance

• Represent evolution in switching capacity, rather than in technology

• With same technology, a later generation switch achieves greater capacity, but at greater
cost
 First generation switch
• Most Ethernet switches and cheap packet routers

• Bottleneck can be CPU, host-adaptor or I/O bus, depending

 First generation switch
Example
• First generation router built with 133 MHz Pentium
– Mean packet size 500 bytes
– Interrupt takes 10 microseconds, word access take 50 ns
– Per-packet processing time takes 200 instructions = 1.504 µs
• Copy loop
register <- memory[read_ptr] memory
[write_ptr] <- register read_ptr <- read_ptr + 4
write_ptr <- write_ptr + 4 counter <-
counter1
if (counter not 0) branch to top of loop
• 4 instructions + 2 memory accesses = 130.08 ns
• Copying packet takes 500/4 *130.08 = 16.26 µs;
interrupt 10 µs
 Second generation switch
• Port mapping intelligence in line cards
• Bottleneck is the bus (or ring)
 Third generation switches
• To overcome the bottleneck in second generation switch (the
bus), third generation switch provides parallel paths (fabric)
Features
•Self-routing fabric
•Output buffer is a point of
contention
•unless we arbitrate access to
fabric
•Potential for unlimited scaling, as long
as we can resolve contention for output
buffer
 Blocking in packet switches
• Can have both internal and output blocking
• Internal
– no path to output
• Output
– trunk unavailable
• Unlike a circuit switch, cannot predict if packets will
blocked (why?)
• If packet is blocked, must either buffer or drop it
 Dealing with blocking
• Over-provisioning
– internal links much faster than inputs
• Buffers
– at input or output
• Backpressure
– if switch fabric doesn’t have buffers, prevent packet from
entering until path is available
• Parallel switch fabrics
– increases effective switching capacity
 Switch fabrics
Crossbar
• Simplest switch fabric

• Used here for packet routing: cross-point is left open long

enough to transfer a packet from an input to an output
• For fixed-size packets and known arrival pattern, can
compute schedule in advance
• Otherwise, need to compute a schedule on-the-fly (what does
the schedule depend on?)
 Switch fabrics
Buffered crossbar

• What happens if packets at two inputs both want to go to same out

– Can defer one at an input buffer

– Or, buffer cross-points

 Switch fabrics
Switch fabric element
• Complicated fabrics can be built from a simple element

• Routing rule: if 0, send packet to upper output, else to lower output

• If both packets to same output, buffer or drop
 Switch fabrics
Effect of packet size on switching fabrics
• A major motivation for small fixed packet size (eg. in ATM) is ease of building large parallel fabrics

• In general, smaller size => more per-packet overhead, but more preemption points/sec

– At high speeds, overhead dominates!

• Fixed size packets helps build synchronous switch

– But we could fragment at entry and reassemble at exit

– Or build an asynchronous fabric

– Thus, variable size doesn’t hurt too much

• Maybe Internet routers can be almost cost-effective as ATM switches

 Buffering
• All packet switches need buffers to match input rate to service rate
– or cause heavy packet loses
• Where should we place buffers?
– input
– in the switch fabric
– output
– shared
 Buffering
Input buffering (input queueing)

• No speedup in buffers or trunks (unlike output queued switch)

• Needs arbiter
• Problem: head of line blocking
– with randomly distributed packets, utilization at most 58.6%
– worse with hot spots
 Buffering
Output queueing

• Don’t suffer from head-of-line blocking. But output buffers need to run much faster than
trunk speed (why?)
• Can reduce some of the cost by using the knockout principle
 unlikely that all N inputs will have packets for the same output
 drop extra packets, fairly distributing losses among inputs
 Buffering
Shared memory

• Route only the header to output port

• Bottleneck is time taken to read and write multi-ported memory
• Doesn’t scale to large switches
• But can form an element in a multistage switch
Buffering Datapath: clever shared memory design

• Reduces read/write cost by doing wide reads and writes

 Buffering
Buffered fabric
• Buffers in each switch element

• Pros _Speed up is only as much as fan-in

– Hardware backpressure reduces buffer requirements

• Cons

– costly (unless using single-chip switches)

– scheduling is hard
Hybrid solutions

• Buffers at more than one point

• Becomes hard to analyze and manage

• But common in practice

 Case Study: ATM
• Asynchronous Transfer Mode (ATM) switches are categorized based on internal architectural
characteristics
– Example: shared memory switch
• Connection-oriented networks
• All information must be divided into fixed-length very small packets called cell (53 bytes).
(Why?)
• The setup gives a chance for negotiating parameters between user requirement
and network commitment, resources are allocated along the path
• The connection is defined by a chain of local identifiers VCIs.
• Assume low-error rate optical channel, so error control is done only end-to-end
• Two key features of a switch design are the switch fabric and the buffer organization
 A Classification Scheme
 ATM switch designs can be classified as time-division or space- division switches
 Time-division switches: all cells pass through a common point within the switch en route to
their output points, but do so at different times.
 Space-division switches: all cells pass through the switch at the same time, but do so on
different paths
Time Division Switches
 The two most common types of time division switches are the shared memory switch and the
shared medium switch
 Shared memory switch: there is a common internal buffer in the switch, through which all cells
pass en route to their output ports
 Shared medium switch: there is a common bus in the switch, over which all cells must passen
route to their output ports
Case Study: ATM
Shared Memory Switch

Input
Dual Output
Ported Ports
Ports
Memory
 Case Study: ATM
Shared Memory Switch
 All incoming cells multiplexed into a single stream (common memory)
 Organized into output queues per output port
 Cells retrieved sequentially
 Central controller and memory bandwidth must be very fast (at least N times input port speed)

Shared Medium Switch

 All incoming cells multiplexed across a common medium (bus)

 Cells processed one at a time and Bus must be very fast (at least N times input port speed)
 Case Study: ATM
Shared-medium Packet Switch

OUTPUT 1
INPUT 1 P/S
S/P FIFO

TIME DIVISION BUS

INPUT 2 OUTPUT 2
S/P FIFO P/S

...
...

...
...
...

OUTPUT N
INPUT N FIFO P/S
S/P
 Case Study: ATM
Space Division Switches

 Space Division Switching is a circuit switching technology in which a single transmission path
is accomplished in a switch by using a physically separate set of cross points.
 Space Division Switching can be achieved by using crossbar switch. A crossbar switch is a
metallic cross point or semiconductor gate that can be enabled or disabled by a control unit.
 The Crossbar switch is made by using the semiconductor.
 Space Division Switching has high speed, high capacity, and non-blocking switches.
 Space division switches provide multiple concurrent paths from the input ports to the output
ports.
 Cells coming in on different input ports and heading to different output ports can proceed
through the switch simultaneously on these separate paths, without interfering with each other.
 Space Division Switches can be categorized in two ways:
1. Crossbar Switch
2. Multistage Switch
Crossbar Switch
• The Crossbar switch is a switch that has n input lines and n output lines. The
crossbar switch has n2 intersection points known as cross points.
Disadvantage of Crossbar switch:
• The number of cross points increases as the number of stations is increased.
Therefore, it becomes very expensive for a large switch. The solution to this is to
use a multistage switch.
 Multistage Switch
• Multistage Switch is made by splitting the crossbar switch into the smaller units
and then interconnecting them.
• It reduces the number of cross points.
Main Differences Between Space Division
Switching and Time Division Switching
• The main difference between space division switching and time division
switching:
Space division switching is a technique that can be implemented for both analog and
digital networks.
On the other hand, the time-division switching.

In space division switching, the path established between two devices is continuous
during the exchange whereas in time-division switching signals are sent at fixed
intervals.
Space division switching is instantaneous whereas time-division switching has a
processing delay.
 Cont……
 Space division switching uses Cross points that are not shared whereas
in time-division switching there is no use of Cross points.
 Space division switching is applicable for both analog and digital
networks whereas time-division switching is only for digital networks.
 In space division switching, there is no time difference between the
transfer of the coded values from input to output whereas, in time-
division switching, the coded values are stored and then transferred.
End of Chapter 3

Thank you