Lec04 Decoder

1) Any logic circuit can be represented using only NAND gates by using DeMorgan's theorem to eliminate OR operations. 2) A NAND-only implementation of the Boolean expression F = A + B(C + D) is F = (A NAND (B NAND (C NAND D))) NAND 1. 3) Decoders and encoders are examples of combinational logic circuits that can be implemented using NAND gates.

Uploaded by

Madhav Singh

Available Formats

Download as PPT, PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

28 views

Lec04 Decoder

Uploaded by

Madhav Singh

Available Formats

Download as PPT, PDF, TXT or read online on Scribd

You are on page 1/ 22

NAND-ONLY LOGIC CIRCUITS

Any logic circuits can be transformed to an implementation where only NAND gates (and inverters) are used. The general approach to finding a NAND-gate realization: Use DeMorgans theorem to eliminate all the OR operations.

NAND-ONLY LOGIC CIRCUITS

(Example) F = A + B (C + D ) = A + B (C D) Note that (C D) = C + D and (A X ) = A + X F = (A (B (C D) ) ) Now there is no OR operation in the Boolean expression. Note that A NAND B = (AB)

F= (A (B (CD))) The logic circuit for this function is given by:

We can also use the same procedure to do NOR only gates.

Ch2. Decoder
Dr. Bernard Chen Ph.D.
University of Central Arkansas Spring 2009

Integrated Circuits

An integrated circuit is a piece (also called a chip) of silicon on which multiple gates or transistors have been embedded These silicon pieces are mounted on a plastic or ceramic package with pins along the edges that can be soldered onto circuit boards or inserted into appropriate sockets

Integrated Circuits

SSI, MSI, LSI: They perform small tasks such as addition of few bits. small memories, small processors VLSI Tasks: - Large memory - Complex microprocessors, CPUs

An SSI chip contains independent NAND gates

Examples of Combinational Circuits

a) Decoders b) Encoders c) Multiplexers d) Demultiplexers

Decoder

Accepts a value and decodes it

Output corresponds to value of n inputs

Consists of:

Inputs (n) Outputs (2n , numbered from 0 p 2n - 1) Selectors / Enable (active high or active low)

The truth table of 2-to-4 Decoder

2-to-4 Decoder

The truth table of 3-to-8 Decoder

A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 D0 1 1 1 1 1 1 1 1 D1 D2 D3 D4 D5 D6 D7

3-to-8 Decoder

3-to-8 Decoder with Enable

2-to-4 Decoder: NAND implementation

Decoder is enabled when E=0 and an output is active if it is 0

2-4 Decoder with 2-input and Enable

Decoder Expansion

Decoder expansion Combine two or more small decoders with enable inputs to form a larger decoder

3-to-8-line decoder constructed from two 2-to-4-line decoders

The MSB is connected to the enable inputs if A2=0, upper is enabled; if A2=1, lower is enabled.

Decoder Expansion

Combining two 2-4 decoders to form one 3-8 decoder using enable switch

The highest bit is used for the enables

Combinational Circuit Design with Decoders

Combinational circuit implementation with decoders n A decoder provide 2 minterms of n input variables Since any Boolean function can be expressed as a sum of minterms, one can use a decoder and external OR gates to implement any combinational function.