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address
lines
fD ADDRESS
DECODER
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control
lines

BLOCK DIAGRAM OF AN ADDRESS

DECODER 1
 CS501
Advanced Computer
Architecture

Lecture24

Dr.Noor Muhammad Sheikh

2
Review

3
• Start by thinking of an address
decoder as a big AND gate.

• We will call this a skeleton

address decoder or SAD.

• Write the desired port address in

binary. 4
• Associate the CPU’s address
lines with each bit.

• Those lines which are zero will

be inverted before being fed
into the big AND gate.

• List the relevant control signals

for the system.
5
• Determine whether the decoder
output should be active high or
active low.

• Inver the output of SAD if active

low is required.

6
• Once the logic for the address
decoder is established, the SAD
can be implemented using any
method of the logic design e.g.,
HDL or VHDL.

7
 Problem Statement

Design a 16-bit parallel output

port mapped on address DEh
of the I/O space of the
FALCON-A CPU.

8
• Start with a “big AND gate”
(SAD).

• Write the address to be

decoded (DEh) in binary.

• Thus, DEh → 1101 1110 b.

9
1 1 0 1 1 1 1 0

A7 A6 A5 A4 A3 A2 A1 A0

Address lines A15 .. A8 are

don’t cares, and will not be
used in this design.

10
• A0 and A5 will be applied to
the “big AND gate” after
inversion.

• The remaining address lines

will be connected directly to
the inputs of the SAD.
11
 A0
.
.
.
A5
fD A6
A7

Control
Line

12
 A0
.
.
A5
fD A6
A7

IOW#
Control
Line

13
• The output is a 1 only when the address,
xxxx xxxx 1101 1110 b, is present on the
FALCON-A’s address bus during an I/O
write cycle.

• This situation will take place when the

instruction out reg, addr with addr=DEh
or 222d is executing on the FALCON-A.

• For all other times, the output will be

inactive. 14
 A0
.
.
A5
fD A6
A7

IOW#
Control
Line

15
• For a 16-bit output port, we use two 8-bit
registers to capture data from the
FALCON-A’s data bus.

• The output of the SAD will be connected to

the enable inputs of the two registers.

• The D-inputs of the registers will be

connected to the data bus.

• The Q outputs of the registers will be

connected to the peripheral device.
16
 Problem Statement

Given a 16-bit parallel output port attached

with the FALCON-A CPU .The port is
mapped onto address DEh of the
FALCON-A’s I/O space. Sixteen LED
branches are used to display the data
being received from the FALCON-A’s data
bus.

17
 Continued…
Every LED branch is wired in such a way
that when a 1 appears on the particular
data bus bit, it turns the LED on; a 0
turns it off. Which LEDs will be ON when
the instruction
out r2, 222
executes on the CPU? Assume r2
contains 1234h.

18
• r2 contains 1234h.

• The bit pattern corresponding to this value

will be sent out to the output port at
address 222.

• 222 is the address of the output port for

this example.

• Writing the bit pattern in binary helps to

determine the LEDs which will be ON.
19
Binary equivalent of 1234h:

0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MSB at address DEh LSB at address DFh

20
• The 8-bit register uses lines D15 .. D8 of the FALCON-
A’s data bus.

• This register will be mapped onto the address DEh of the

I/O space.

• The architect of the FALCON-A had chosen:

1): a “byte-wide” organization of the address space,
2): a 16-bit data bus width,
3): the “big-endian” data format
at the ISA design stage.

21
• D15...D8 will transfer the higher
significance byte using the
address DEh.

• D7...D0 will transfer the lower

significance data byte using the
address DFh.

• The LEDs at L12, L9, L5, L4

and L2 will turn on. 22
23
• Consider the execution of the
instruction out r2, 223 assuming r2
contains 1234h.

• This is a 16-bit transfer at address 223

(DFh) and 224 (E0h).

24
 In first case:
where the CPU does not allow the use of
some part of its data bus in a transfer:

• None of the registers will be enabled as a

result of this instruction.

• The reason is that the output of the 8-input

AND gate will be a zero for both
addresses DFh and E0h. So, that output
port cannot be used. 25
 In second case:
where the CPU has allowed to use a portion of
its data bus in an I/O transfer:

• The register at the address DEh will not be

enabled.

• The CPU will send the high data byte(12h) to the

register at the address DFh over data lines D7…
D0.

• The fact that data lines D7…D0 should be used

for the transfer of high byte, will be taken care of
by the hardware.
26
 A Question:

Where the low data byte (i.e. 34h)

present at D15…D8 data lines
would be placed?

• If there exists an output port at

address E0h in the system, then 34h
will be placed there (in the next bus
cycle), otherwise it will be lost.
27
• A possible option for the architect
in this case would be to revisit the
design steps and allow the use of
part of the CPU registers, for I/O
transfers.

28
• The following instructions will
access the output port at the
address 0FEF2h.

mov dx, 0FEF2h

mov al, 12h
out dx, al
29
30
• Turn on all the 16 LEDs one by one
on output port of our example.
Each LED should stay on for a
noticeable amount or time Report
after the last LED is Turned on

31
; filename: IO2_eg3.asmfa
;
;ALL LEDS ARE turned Off initially
;
movi r1,0
out r1,222
;
;First LED will be turned on each time
;
start: movi r1,1
out r1,222
;
movi r5,15 32
;
;DELAY LOOP
;
delay1: movi r2,0
again1: subi r2,r2,1
jnz r2, [again1]
;
movi r3,0 ; TURN OFF ALL LEDS
out r3,222
;
delay2: movi r2,0
again2: subi r2,r2,1
jnz r2, [again2] 33
;
shiftl r1,r1,1 ; next LED ON
out r1,222
subi r5,r5,1
jnz r5, [delay1]
jump [start]
halt

34
 Start

allInitialize
LEDs off at DEh
All LEDs off at DEh

Turn on right most LED

wait

Turn off all LEDs

wait

Turn on next LED on the left

Y leftmost N
LED
lits?
35
• The first two instructions turn all the
LEDs off by sending a 0 to each bit of
the output port.
mov r1,0
out r1,222

• Then a 1 is sent to L0 causing it to turn

on.

• The program enters a loop to cause the

other LEDs (L1 through L15) to turn on,
one by one in sequence. 36
• The following three instructions
introduce a delay between
successive bit patterns sent to
the output port:

delay1: movi r2,0

again1: subi r2,r2,1
jnz r2,[again1]
37
• Starting with a value of 0 in r2 this
value is decremented to FFFFh when
the again1 loop is entered.

• The jnz instruction will cause r2 to

decrement again and again.

• This executes the loop 65,535 times.

38
• After the delay, all the LEDs are
turned off.

• Then a second delay loop executes.

• Finally, the next LED on the left is

turned on by the following two
instructions:
shiftl r1,r1,1
out r1, 222 39
• After the left most LED is turned on,
the process starts all over again.

40
 Execution Time
ET = CPI x IC x T = CPI x IC / f
where
CPI = clocks per instruction
IC = instruction count
T = time period of the clock, and
f = frequency of the clock.

Using the assumed values, we get

ET = (3+4) x 65535 / (1x106 ) = 0. 459 sec
41