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DFT basics 1

The document discusses Design For Testability (DFT), a methodology essential for ensuring that integrated circuits can be efficiently tested for defects. It covers concepts such as scan chains, Automatic Test Pattern Generation (ATPG), and the importance of fault models like stuck-at faults in the testing process. Additionally, it highlights the benefits of scan chain reordering to optimize design performance by reducing routing congestion and improving timing.

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14 views

DFT basics 1

The document discusses Design For Testability (DFT), a methodology essential for ensuring that integrated circuits can be efficiently tested for defects. It covers concepts such as scan chains, Automatic Test Pattern Generation (ATPG), and the importance of fault models like stuck-at faults in the testing process. Additionally, it highlights the benefits of scan chain reordering to optimize design performance by reducing routing congestion and improving timing.

Uploaded by

bhavanireddy.cbr
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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DFT basics/ Scan Chain

reordering
Introduction:-
The chip manufacturing process is prone to defects and the defects are
commonly referred as fault.
To make the task of detecting as many faults as possible in a design, we
need to add additional logic called DFT.
What is DFT..??
• Design For Testability.
• In the process of designing complex Ics, it is essential to ensure that
the chips can be thoroughly tested to identify and fix any potential
defects.
• It provides a set of techniques and methodologies that enable the
efficient testing of these circuits.
• Helps identify issues such as functional faults, manufacturing defects
and timing errors.
Importance of DFT:
• Enables efficient testing, reducing the time and cost involved in the
testing phase of chip development.
• Without proper DFT measures, identifying and fixing defects becomes
challenging, leading to delays in product launches and potential
financial losses.
• It empowers designers with the ability to observe and control the
internal states of the circuit during testing.
• This visibility allows for more accurate fault diagnosis and facilitates
further improvements in the design process.
Scan and ATPG:-
Fault models:-
It abstracts the behaviour of manufacturing defects so that test vectors
can be generated to detect them.
• Functional defects: Stuck-at Fault Model
• Current defects: Pseudo Stuck-at Fault Model
• Speed defects: At-speed Fault Model, Path delay fault model
Stuck-at faults:-
• This is the most common fault model used in industry.
• It models manufacturing defects which occurs when a circuit node is
shorted to VDD (stuck-at-1 fault) or GND (stuck-at-0 fault)
permanently.
• The fault can be at the input or output of a gate. Thus a simple 2-input
AND gate has six possible stuck-at faults.
• In the circuit shown below, suppose we have a stuck-at-0 fault at the
output of an AND gate.
• Note one important thing, there are three input ports in the circuit, thus
we can have a combination of eight different inputs or patterns {000,
001, 010, 011, 100, 101, 110, 111}; out of the eight patterns, only two
patterns {011, 111} will be able to detect this fault because with rest of
the patterns the expected output will be same as the actual circuit
output in the presence of this s-a-0 fault.
• The ATPG tools will try to generate the stuck-at fault patterns required to
test all the possible fault locations using complex algorithms, but if it is
unable to find patterns for few faults, then it will classify those faults as
untestable.
• Scan is the internal modification of the design’s circuitry to increase its
test-ability. ATPG stands for Automatic Test Pattern Generation; as the
name suggests, this is basically the generation of test patterns. In other
words, we can say that Scan makes the process of pattern generation
easier for detection of the faults we discussed earlier.

Fig: A typical sequential circuit (before scan insertion)


• To test a fault we need to initialize the flops to the required values as
we had shown while discussing about stuck-at faults and at-speed
faults. In a bigger sequential circuit (without scan), it is difficult to
control the flop’s value through primary inputs and observe the
captured response in primary outputs. To solve this issue we do ‘Scan
Insertion’ during synthesis.
• The goal of ‘Scan Insertion’ is to make a difficult-to-test sequential
circuit behave (during testing process) like an easier-to-test
combinational circuit. Achieving this goal involves two steps –
1. Converting regular flop to scan flop:-
• All the flops in the design are converted into scan flops (as shown in
Figure) except –
• The ones that are excluded by user. These are called non-scan
flops.
• The ones that have DFT DRC violation(s).

Fig : regular flop vs Scan flop


2. Stitching the Scan Flops to form Scan Chains:-
The scan flops are stitched to form scan chain(s) (as shown in
Figure). The number of scan chains depends upon various user
inputs like –
• Length of scan chain
• Clock domain mixing
• Power domain mixing
• Voltage domain mixing
Figure : A typical sequential circuit compatible for Scan and ATPG (after scan insertion)
• Thus in a way, we can say the scan flop’s output (Q) act as pseudo
primary output of the design and the scan flop’s input (D) act as
pseudo primary inputs to the design, thereby making it a pseudo
combination circuit.
• The expected responses along with the patterns are then stored in
the memory of Automatic Test Equipment (ATE).
• In post-silicon, the manufactured chip is tested using the ATE, which
loads the pattern and compares it with the expected response for
pass or fail status.
Fig : A schematic showing how testing works
Scan chain reordering:-
• Scan chain reordering is an optimization technique to ensure scan
chains are connected in more efficient way – based upon the
placement of the flip-flops. At initial stage , we do not have the
placement information, so we just stitch the flops register by register.
The tools will stitch the flops randomly to form a scan chain before
placement.
• But after placement it might be possible that the two flops stitched at
initial stage of a different block sits far from each other when the
placement is done. So if we keep the same scan chain order, we will
face the placement congestion and timing congestion and more
routing resources are required.
• In order to avoid the congestion before placement we have to
follow the below steps
• Disconnect the scan chain in the designing.
• Based on the timing and congestion the tool optimizes the
standard cells
• Once the placement was done, reordering of scan chains are
done based on the timing and placement congestion in design
by maintaining the same number of scan cells .
Advantages of Scan chain
Reordering:-
• Reduced routing congestion
• Improved timing
• Optimized resource utilization
• Enhanced design performance

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