MODULE II

8051 INSTRUCTIONS MPMC Sec A

School of Electronic
Ananya Sciences
Dastidar
 Instruction Timings
The 8051 internal operations and external

INSTRUCTION SET
read/write operations are controlled by the oscillator
clock.
T-state, Machine cycle and Instruction cycle are
terms used in instruction timings.
T-state is defined as one subdivision of the
operation performed in one clock period.
The terms 'Tstate' and 'clock period' are often used
synonymously.
Machine cycle is defined as 12 oscillator
periods.
A machine cycle consists of six states and each
state lasts for two oscillator periods or 2 Tstates.
An instruction takes one to four machine
cycles to execute an instruction.
Instruction cycle is defined as the time required for
completing the execution of an instruction.
The 8051-instruction cycle consists of one to four
AN EXAMPLE
If 8051 microcontroller is operated with 12 MHz oscillator, find the
execution time for the following four instructions.
1. ADD A, 45H 2. SUBB A, #55H 3. MOV DPTR, #2000H
4. MUL AB

Since the oscillator frequency is 12 MHz, the clock period is, Clock period =
1/12 MHz = 0.08333 µS. Time for 1 machine cycle = 0.08333 µS x 12 =1 µS.
Instruction No. of machine cycles Execution time
1. ADD A, 45H 1 1 µs
2. SUBB A, #55H 2 2 µs
3. MOV DPTR, #2000H 2 2 µs
4. MUL AB 4 4 µs
8051 INSTRUCTIONS
The instructions of 8051 can be broadly classified under the
following headings.
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branch instructions
5. Subroutine instructions
6. Bit manipulation instructions
DATA TRANSFER
INSTRUCTIONS
In this group, the instructions perform data transfer operations of the
following types.
a. Move the contents of a register Rn to A
i. MOV A,R2 ii. MOV A,R7

b. Move the contents of a register A to Rn

i. MOV R4,A ii. MOV R1,A

c. Move an immediate 8 bit data to register A or to Rn or to a memory

location(direct or indirect)
i. MOV A, #45H ii. MOV R6, #51H iii. MOV 30H, #44H
iv. MOV @R0, #0E8H v. MOV DPTR, #0F5A2H vi. MOV DPTR, #5467H
DATA TRANSFER
INSTRUCTIONS
d. Move the contents of a memory location to A or A to a memory
location using direct and indirect addressing
i. MOV A, 65H ii. MOV A, @R0
iii. MOV 45H, A iv. MOV @R1, A

e. Move the contents of a memory location to Rn or Rn to a

memory location using direct addressing
i. MOV R3, 65H ii. MOV 45H, R2
DATA TRANSFER
INSTRUCTIONS
f. Move the contents of memory location to another memory location
using direct and indirect addressing
i. MOV 47H, 65H ii. MOV 45H, @R0

g. Move the contents of an external memory to A or A to an external

memory
i. MOVX A,@R1 ii. MOVX @R0,A
iii. MOVX A,@DPTR iv. MOVX@DPTR,A

h. Move the contents of program memory to A

i. MOVC A, @A+PC ii. MOVC A, @A+DPTR
DATA TRANSFER
INSTRUCTIONS
i. Push and Pop instructions
[SP]=07 //CONTENT OF SP IS 07 (DEFAULT VALUE)
MOV R6, #25H [R6]=25H //CONTENT OF R6 IS 25H
MOV R1, #12H [R1]=12H //CONTENT OF R1 IS 12H
MOV R4, #0F3H [R4]=F3H //CONTENT OF R4 IS F3H
PUSH 6 [SP]=08 [08]=[06]=25H //CONTENT OF 08 IS 25H
PUSH 1 [SP]=09 [09]=[01]=12H //CONTENT OF 09 IS 12H
PUSH 4 [SP]=0A [0A]=[04]=F3H //CONTENT OF 0A IS F3H
POP 6 [06]=[0A]=F3H [SP]=09 //CONTENT OF 06 IS F3H
POP 1 [01]=[09]=12H [SP]=08 //CONTENT OF 01 IS 12H
POP 4 [04]=[08]=25H [SP]=07 //CONTENT OF 04 IS 25H
DATA TRANSFER
INSTRUCTIONS
j. Exchange instructions The content of source ie., register, direct
memory or indirect memory will be exchanged with the contents of
destination ie., accumulator.
i. XCH A,R3 ii. XCH A,54h iii. XCH A,@R1

k. Exchange digit. Exchange the lower order nibble of Accumulator

(A0-A3) with lower order nibble of the internal RAM location which is
indirectly addressed by the register.
i. XCHD A,@R1 ii. XCHD A,@R0
DATA TRANSFER
INSTRUCTIONS
ARITHMETIC INSTRUCTIONS:
ADDITION
The 8051 can perform addition, subtraction. Multiplication and
division operations on 8-bit numbers.
In the addition group, we have instructions to
a. Add the contents of A with immediate data without or with carry.
i. ADD A, #45H ii. ADDC A, #0B4H
b. Add the contents of A with register Rn without or with carry.
i. ADD A, R5 ii. ADDC A, R2
c. Add the contents of A with contents of memory without or with
carry using direct and indirect addressing
i. ADD A, 51H ii. ADDC A, 75H
iii. ADD A, @R1 iv. ADDC A, @R0
CY AC and OV flags will be affected by this operation.
ARITHMETIC INSTRUCTIONS:
SUBTRACTION
In this group, we have instructions to
a. Subtract the contents of A with immediate data.
i. SUBB A, #45H ii. SUBB A, #0B4H
b. Subtract the contents of A with register Rn.
i. SUBB A, R5 ii. SUBB A, R2
c. Subtract the contents of A with contents of
memory using direct and indirect addressing
i. SUBB A, 51H ii. SUBB A, @R1
CY AC and OV flags will be affected by this
operation.
ARITHMETIC INSTRUCTIONS:
MULTIPLICATION
MUL AB
This instruction multiplies two 8 bit unsigned numbers which are
stored in A and B register.
After multiplication the lower byte of the result will be stored in
accumulator and higher byte of result will be stored in B register.
Eg.
MOV A,#45H ; [A]=45H
MOV B,#0F5H ; [B]=F5H
MUL AB ; [A] x [B] = 45 x F5 = 4209 ; [A]=09H,
[B]=42H
ARITHMETIC INSTRUCTIONS:
DIVISION DIV AB
This instruction divides the 8-bit unsigned number which is stored
in A by the 8-bit unsigned number which is stored in B register.
After division the result will be stored in accumulator and remainder
will be stored in B register.
Eg.
MOV A,#45H ; [A]=0E8H
MOV B,#0F5H ; [B]=1BH
DIV AB ; [A] / [B] = E8 /1B = 08 H with remainder 10H ;
[A] = 08H, [B]=10H
ARITHMETIC INSTRUCTIONS:
DECIMAL ADJUST AFTER
ADDITION
DA A
When two BCD numbers are Eg 1:
added, the answer is a non-BCD MOV A, #23H
number. MOV R1, #55H
To get the result in BCD, we use ADD A, R1 // [A]=78
DA A instruction after the DA A // [A]=78 no changes in the accumulator
addition. after DA A
DA A works as follows. Eg 2:
 If lower nibble is greater than MOV A, #53H
9 or auxiliary carry is 1, 6 is MOV R1, #58H
added to lower nibble. ADD A, R1 // [A] = ABh
 If upper nibble is greater than DA A // [A] = 11, C = 1 .
9 or carry is 1, 6 is added to ANSWER IS 111.
upper nibble. Accumulator data is changed after DA A
ARITHMETIC INSTRUCTIONS:
INCREMENT
INC increments the value of the operand by one.
INC A //If the initial value of register is FFh, incrementing the value will
cause it to reset to 0. The Carry Flag is not set when the value "rolls over"
from 255 to 0.
INC Rn
INC DIRECT
INC @Ri
INC DPTR // the value two-byte unsigned integer value of DPTR is
incremented. If the initial value of DPTR is FFFFh, incrementing the value
will cause it to reset to 0.
ARITHMETIC INSTRUCTIONS:
DECREMENT
DEC decrements the operand by one.
DEC A
DEC Rn
DEC DIRECT
DEC @Ri

If the initial value of is 0, decrementing the value will cause it to

reset to FFh. The Carry Flag is not set when the value "rolls over"
from 0 to FFh.
LOGICAL INSTRUCTIONS:
LOGICAL AND
ANL destination, source: ANL does a bitwise "AND" operation
between source and destination, leaving the resulting value in
destination.
The value in source is not affected.
 "AND" instruction logically AND the bits of source and destination.
ANL A,#DATA
ANL A, Rn
ANL A,DIRECT
ANL A,@Ri
ANL DIRECT,A
ANL DIRECT, #DATA
LOGICAL INSTRUCTIONS:
LOGICAL
 OR
ORL destination, source: ORL does a bitwise "OR" operation
between source and destination, leaving the resulting value in
destination.
The value in source is not affected.
" OR " instruction logically OR the bits of source and destination.
ORL A,#DATA
ORL A, Rn
ORL A,DIRECT
ORL A,@Ri
ORL DIRECT,A
ORL DIRECT, #DATA
LOGICAL INSTRUCTIONS:
LOGICAL EX-OR
XRL destination, source: XRL does a bitwise "EX-OR" operation between
source and destination, leaving the resulting value in destination.
The value in source is not affected.
" XRL " instruction logically EX-OR the bits of source and destination.
XRL A,#DATA
XRL A,Rn
XRL A,DIRECT
XRL A,@Ri
XRL DIRECT,A
XRL DIRECT, #DATA
LOGICAL INSTRUCTIONS:
LOGICAL NOT
CPL complements operand, leaving the result in operand.
If operand is a single bit then the state of the bit will be reversed.
If operand is the Accumulator then all the bits in the Accumulator
will be reversed.
CPL A
CPL C
CPL bit address
LOGICAL INSTRUCTIONS:
SWAP
SWAP A – Swap the upper nibble and lower nibble of A.
 ROTATE INSTRUCTIONS
RR A This instruction is rotate right the accumulator.
D D D D D D D D
7 6 5 4ACC3 2 1 0
Each bit is shifted one location to the right, with bit 0 going to bit 7.

RL A Rotate left the accumulator.

D to
Each bit is shifted one location to the left, with bit 7 going D bit
D0 D D D D D
7 6 5 ACC 4 3 2 1 0
RRC A Rotate right through the carry.
Each bit is shifted one location to the right, with bit 0 going into the
carry bit in the PSW, while the carry was at goes into bit
D D
7 D D D D D D C
7 6 5 4 3 2 1 0 Y
RLC A Rotate left through the carry. ACC
Each bit is shifted one location to the left, with bit 7 going into the carry
bit in the PSW, while the carry goes into bit 0
D D D D D D D D C
7 6 5 4 3 2 1 0 Y
ACC
BRANCH (JUMP)
INSTRUCTIONS
Jump and Call Program Range
There are 3 types of jump instructions. They are:-
1. Relative Jump
2. Short Absolute Jump
3. Long Absolute Jump
 List of Branching
Instructions in 8051
Ope Mne
rati moni Description
on cs
ACAL Calls a subroutine
L in the maximum
Addr address range of
ess112K bytes
Call
LCAL Calls a subroutine
L in the maximum
Addr address range of
ess1664K bytes
Returns the
RET control from
subroutine
Retu
Returns the
List of Branching Instructions in
8051
AJMP Address11 Jumps to an address in a 2KB range
LJMP Address16 Jumps to an address in a 64KB range
Jumps to an address in a 256-byte range (0 to
SJMP Relative address
127 (0-7FH) range and -1 to -128 (FFH-80H).
JMP @A+DPTR [DPTR]<-[DPTR+A]
JZ Relative address Jumps to address when accumulator=0
JNZ Relative address Jumps to address when accumulator!=0
CJNE A, Direct address, Relative Jumps to relative address when
address accumulator=data stored at a direct address
Jump
Jumps to relative address when
CJNE A, #Data,Relative address
accumulator=data given by the programmer
Jumps to relative address when data at
CJNE @Rn, #Data,Relative address memory location stored in register=data given
by the programmer
Decrements value in Rn and jump to relative
DJNZ Rn, Relative address
address till Rn!=0
Decrements value at memory location stored
DJNZ Direct address, Relative
in a register and jump to relative address till
address
memory location stored in register =0
SHORT ABSOLUTE JUMP
In this case only 11bits of the absolute  It can be seen that the upper 5bits
jump address are needed.
The absolute jump address is
of the program counter (PC) hold the
calculated in the following manner. page number and the lower 11bits of
In 8051, 64 kbyte of program memory the PC hold the address within that
space is divided into 32 pages of 2 page.
kbyte each.
 Thus, an absolute address is formed
The hexadecimal addresses of the
pages are given as follows:- by taking page numbers of the
Page (Hex) Address (Hex)
instruction (from the program
00 0000 - 07FF counter) following the jump and
01 0800 - 0FFF attaching the specified 11bits to it to
02 1000 - 17FF form the 16-bit address.
03 1800 - 1FFF  Advantage: The instruction length
..
1E F000 - F7FF
becomes 2 bytes.
1F F800 - FFFF  Example of short absolute jump: -
CONDITIONAL JUMP
INSTRUCTIONS
2. Conditional Jump instructions.
JBC Jump if bit ＝ 1 and clear bit
JNB Jump if bit ＝ 0 JB Jump if bit ＝ 1
JNC Jump if CY ＝ 0 JC Jump if CY ＝ 1
CJNE reg,#data Jump if byte ≠ #data
CJNE A,byte Jump if A ≠ byte
DJNZ Decrement and Jump if A ≠ 0
JNZ Jump if A ≠ 0
JZ Jump if A ＝ 0
All conditional jumps are short jumps.
BIT LEVEL JUMP
INSTRUCTIONS
Bit level JUMP instructions will check the conditions of the
bit and if condition is true, it jumps to the address specified
in the instruction. All the bit jumps are relative jumps.
JB bit, rel ; jump if the direct bit is set to the relative
address specified.
JNB bit, rel ; jump if the direct bit is clear to the relative
address specified.
JBC bit, rel ; jump if the direct bit is set to the relative
address specified and then clear the bit
BIT MANIPULATION
INSTRUCTIONS
8051 has 128 bit addressable memory. Bit addressable SFRs and bit addressable PORT pins. It is possible to
perform following bit wise operations for these bit addressable locations.
1. LOGICAL AND
a. ANL C, BIT(BIT ADDRESS) ; ‘LOGICALLY AND’ CARRY AND CONTENT OF BIT ADDRESS, STORE RESULT IN
CARRY
b. ANL C, /BIT; ; ‘LOGICALLY AND’ CARRY AND COMPLEMENT OF CONTENT OF BIT ADDRESS, STORE RESULT IN
CARRY
2. LOGICAL OR
a. ORL C,BIT(BIT ADDRESS) ; ‘LOGICALLY OR’ CARRY AND CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY
b. ORL C, /BIT; ; ‘LOGICALLY OR’ CARRY AND COMPLEMENT OF CONTENT OF BIT ADDRESS, STORE RESULT IN
CARRY
3. CLR bit
a. CLR bit ; CONTENT OF BIT ADDRESS SPECIFIED WILL BE CLEARED.
b. CLR C ; CONTENT OF CARRY WILL BE CLEARED.
4. CPL bit
a. CPL bit ; CONTENT OF BIT ADDRESS SPECIFIED WILL BE COMPLEMENTED.
b. CPL C ; CONTENT OF CARRY WILL BE COMPLEMENTED
CLEAR OPERATION
Flags affected
Descripti Executio
Opcode Operand Size Auxilary
on n Time Carry Overflow
carry
Clears the
data
stored in
12 clock Unaffecte Unaffecte
C the CY 1 byte set to 0
cycles d d
flag of the
accumulat
CLR or
Clears the
data bit
stored at 12 clock Unaffecte Unaffecte Unaffecte
Address 2 bytes
a cycles d d d
particular
CLR C; Clears the data in the CY flag of the PSW register
address
CLR P1.7; Clears the bit at port 1.7
 Complement instruction
Flags affected
Execution
Opcode Operand Description Size Auxilary
Time Carry Overflow
carry
Complemen
ts the data
stored in
12 clock Unaffecte Unaffecte
C the CY flag 1 byte Affected
cycles d d
of the
accumulato
CPL
r
Complemen
ts the data
12 clock Unaffecte Unaffecte Unaffecte
Address bit stored at 2 bytes
cycles d d d
a particular
address
CPL C; Complements the value stored in the carry flag
CPL TF1; Complements the TF1 flag in TCON register
SET BIT
Flags affected
Descripti Executio
pcode Operand Size Auxilary
on n Time Carry Overflow
carry
Sets the
data
stored in
the CY 12 clock Unaffecte Unaffecte
C 1 byte 1
flag of the cycles d d
PSW
register to
SETB 1
Sets the
data bit
stored
SETB C; Sets the value inat
the carry flag 12
to clock
1 Unaffecte Unaffecte Unaffecte
Address a 2 bytes
SETB TR1; Sets the value of TR1 flag incycles
TCON register to 1(used
d d to startd the timer)
particular
address to
1
AND OPERATION
Flags affected
Opco Execution
Operand Description Size Auxilary
de Time Carry Overflow
carry
Performs AND
operation
between the
C, 24 clock
data stored in 2 byte Affected Unaffected Unaffected
Address cycles
the carry flag
and the given
address
Performs AND
ANL
operation
between the
data stored in
C, 24 clock
the carry flag 2 bytes Unaffected Unaffected Unaffected
/Address cycles
and the
complement of ANL C, 09H
the data at any ANL C, /05H
given address
 OR OPERATION
Opera Execution
Flags affected
Opode Description Size Auxilary
nd Time Carry Overflow
carry
Performs OR operation
C,
between the data stored 24 clock Unaffecte
Addres 2 byte Affected Unaffected
in the carry flag and the cycles d
s
given address
ORL Performs OR operation
C, between the data stored
2 24 clock Unaffect Unaffecte
/Addre in the carry flag and the Unaffected
bytes cycles ed d
ss complement of the data at
any given address
ORL C, 09H
ORL C, /07H
INSTRUCTION TYPES
The Op-Code part of the instruction contains the Mnemonic, which
specifies the type of operation to be performed. All Mnemonics or the
Opcode part of the instruction are of One Byte size.
Coming to the Operand part of the instruction, it defines the data being
processed by the instructions. The operand can be any of the following:
•No Operand
•Data value
•I/O Port
•Memory Location
•CPU register
DATA TRANSFER
ARITHMETIC
LOGICAL
BOOLEA
N OR BIT
MANIPUL
ATION
BRANCHING
TIMING DIAGRAM
1 BYTE AND TWO BYTE
END OF SLIDES