EC 311 – Introduction to Logic Design

Lecture 21
Finite State Machines
Memory
11/20/2024

Prof. Rabia Yazicigil Kirby

 Moore vs. Mealy FSMs
Mealy FSM adds this

Controller Output Output

logic O logic O
I O
FSM FSM
Combinational
FSM FSM outputs outputs
logic I I
inputs outputs
S FSM Next-state FSM Next-state
m logic inputs logic
inputs
m-bit m S S
clk
state register

N clk State register clk State register

N N
(a) (b)

• FSM implementation architecture

– State register and logic Inputs: b; Outputs: x
– More detailed view /x=0
• Next state logic – function of present state and FSM inputs
S0 S1
• Output logic
–If function of present state only – Moore FSM b/x=1
–If function of present state and FSM inputs – Mealy FSM b’/x=0
Graphically: show outputs with
transitions, not with states
Digital Design 2e
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Frank Vahid
 Mealy FSMs May Have Fewer States
enough: enough money for soda
Inputs: enough (bit) Inputs: enough (bit) d: dispenses soda
Outputs: d, clear (bit) Outputs: d, clear (bit)
clear: resets money count
/ d=0, clear=1

Init Wait Init Wait

d=0 enough¢ enough¢
enough
clear=1
Disp enough/d=1
d=1

clk clk
Inputs: enough Inputs: enough
State: I W W D I State: I W W I

Outputs: clear Outputs: clear

d d
(a) (b)

• Soda dispenser example: Initialize, wait until enough, dispense

– Moore: 3 states; Mealy: 2 states

Digital Design 2e
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Frank Vahid
 Mealy vs. Moore
Inputs: b; Outputs: s1, s0, p Inputs: b; Outputs: s1, s0, p
• Q: Which is Moore, b’
Time b’/s1s0=00, p=0 Time
and which is Mealy? b/s1s0=00, p=1 b
s1s0=00, p=0
• A: Mealy on left, Moore on
Alarm S2 s1s0=00, p=1
right b’/s1s0=01, p=0
b
– Mealy outputs on b/s1s0=01, p=1
Alarm
b’

arcs, meaning Date b’/s1s0=10, p=0 s1s0=01, p=0

b
outputs are function b/s1s0=10, p=1
S4 s1s0=01, p=1
of state AND INPUTS Stpwch b’/s1s0=11, p=0 b
b’
– Moore outputs in b/s1s0=11, p=1 Date
s1s0=10, p=0
states, meaning Mealy
b
S6 s1s0=10, p=1
outputs are function
b
of state only b’
Stpwch
s1s0=11, p=0
b
Example is wristwatch: pressing S8 s1s0=11, p=1
button b changes display (s1s0) Moore
Digital Design 2e
and also causes beep (p=1)
Copyright © 2010
Frank Vahid Assumes button press is synchronized to occur for one cycle only
 Mealy vs. Moore Tradeoff
• Mealy may have fewer states, but drawback is that its outputs change mid-cycle if
input changes
– Note earlier soda dispenser example
• Mealy had fewer states, but output d not 1 for full cycle
– Represents a type of tradeoff

Inputs: enough (bit) Inputs: enough (bit)

Outputs: d, clear (bit) Outputs: d, clear (bit)
/d=0, clear=1

Moore Init Wait Init Wait Mealy

enough’
d=0 enough’
enough
clear=1
Disp enough/d=1
d=1

clk clk

Inputs: enough Inputs: enough

State: I W W D I State: I W W I

Outputs: clear Outputs: clear

Digital Design 2e d d
Copyright © 2010
Frank Vahid (a) (b)
 Implementing a Mealy FSM
• Straightforward Inputs: enough (bit)
Outputs: d, clear (bit)
– Convert to state table / d=0, clear=1

– Derive equations for Init Wait

enough’/d=0
each output enough/d=1
– Key difference from
Moore: External
outputs (d, clear)
may have different
value in same state,
depending on input
values
Digital Design 2e
Copyright © 2010
Frank Vahid
 Mealy and Moore can be Combined

Inputs: b; Outputs: s1, s0, p

b’/p=0
Time
s1s0=00
b/p=1 Easier to comprehend
b’/p=0 Combined due to clearly
Alarm Moore/Mealy associating s1s0
s1s0=01 FSM for beeping assignments to each
b/p=1
wristwatch state, and not duplicating
b’/p=0 s1s0 assignments on
Date example
outgoing transitions
s1s0=10
b/p=1
b’/p=0
Stpwch
s1s0=11
b/p=1

Digital Design 2e
Copyright © 2010
Frank Vahid
 Basic Register
• Typically, we store multi-bit items
– e.g., storing a 4-bit binary number
• Register: multiple flip-flops sharing clock signal
– From this point, we’ll use registers for bit storage
• No need to think of latches or flip-flops
• But now you know what’s inside a register
I3 I2 I1 I0
4-bit register
D D D D I3 I2 I1 I0
Q Q Q Q reg(4)
clk Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

Digital Design 2e
Copyright © 2010
Frank Vahid
Register Examples
 Random Access Memory (RAM)
• RAM – Readable and writable memory 32 32
W_data R_data
– “Random access memory” 4 4
• Strange name—Created several decades ago to contrast W_addr R_addr
with sequentially-accessed storage like tape drives W_en R_en
– Logically same as register file—Memory with address ×
16 32
register file
inputs, data inputs/outputs, and control
• RAM usually one port; RF usually two or more Register file from Chpt. 4

– RAM vs. RF
• RAM typically larger than about 512 or 1024 words
32
• RAM typically stores bits using a bit storage approach data
that is more efficient than a flip-flop 10
addr
• RAM typically implemented on a chip in a square rather 1024× 32
rw RAM
than rectangular shape—keeps longest wires (hence
delay) short en

RAM block symbol

Digital Design 2e
Copyright © 2010
Frank Vahid
 RAM Internal Structure
Let A = log2M wdata(N-1)wdata(N-2)
wdata0
32
data
10 word bit storage
addr block
1024x32 enable
rw RAM d0 (aka “cell”)
en
addr0 a0 word
addr1 a1 AxM
d1
decoder
addr(A-1) a(A-1) data cell
word word
e d(M-1) enableenable
clk
Combining rd and wr rw data
en
data lines rw to all cells
wdata

rdata0

wdata0
rdata
(N-1)

(N-1)

rdata(N-1)rdata(N-2)rdata0
RAM cell
rw

data(N-1) data0 • Similar internal structure as register file

– Decoder enables appropriate word based on address inputs
– rw controls whether cell is written or read
– rd and wr data lines typically combined
– Let’s see what’s inside each RAM cell
Digital Design 2e
Copyright © 2010
Frank Vahid
 Static RAM (SRAM) SRAM cell
data data’

wdata(N-1) wdata(N-2) wdata0

cell
32 Let A =log2 M d d’
data word bit storage
10 enable block ,, ,,
addr d0 (aka cell )
1024x32 a0
a
addr0 word
rw RAM addr1 a1 A × M
d1

addr
decoder
en addr(A-1) a(A-1) data cell

word word word 0

e d(M-1) enable enable
clk
rw data
enable
en
rw to all cells

rdata(N-1) rdata(N-2) rdata0 SRAM cell

data data’
• “Static” RAM cell 1 0
– 6 transistors (recall inverter is 2 transistors) d
a
– Writing this cell 1 0
• word enable input comes from decoder
• When 0, value d loops around inverters
word 1
– That loop is where a bit stays stored enable
• When 1, the data bit value enters the loop
– data is the bit to be stored in this cell data data’
– data’ enters on other side cell
d d’
– Example shows a “1” being written into cell 1 0 a

word 0
enable
Digital Design 2e
Copyright © 2010
Frank Vahid
 Static RAM (SRAM)
wdata(N-1) wdata(N-2) wdata0
32 Let A =log2 M
data word bit storage
10 enable block ,, ,,
addr d0 (aka cell )
1024x32 addr0 a0 word
rw RAM addr1 a1 A × M
d1

addr
decoder
en addr(A-1) a(A-1) data cell

word word
e d(M-1) enable enable
clk
rw data
en
rw to all cells

• “Static” RAM cell rdata(N-1) rdata(N-2) rdata0

SRAM cell
– Reading this cell data data’
1 1
• Somewhat trickier
d
• When rw set to read, the RAM logic sets both data and
data’ to 1 1 0
• The stored bit d will pull either the left line or the right
a
bit down slightly below 1
• “Sense amplifiers” detect which side is slightly pulled 1 1 <1
word
down enable
– The electrical description of SRAM is really beyond To sense amplifiers
our scope – just general idea here, mainly to contrast
with DRAM...

Digital Design 2e
Copyright © 2010
Frank Vahid