Computer Organization and

Assembly Language
Week 1
Lecture 02: System Bus structure
Instructor: Engr. Iqra Saleem
Email: [email protected]
UNIVERSITY OF HARIPUR
Basic Computer Architecture
• A computer system comprises of processor, memory and I/O devices.
• I/O is used for interfacing with external world, while memory is the
processor’s internal world.
• Processor is the core and is responsible for performing operations.
• The operation of computer can be fairly describe with a processor and
memory only
Structure -Top Level
Basic Computer Organization
Basic Computer Organization
• The scenario that the processor executes the
operations and the memory contains data
elements requires the mechanism for the
processor to read that data from the memory
which is a dumb device.
• Just like a postman, who must be told the precise
address on the letter, to inform him where the
destination is located.
• If we only want to read the data and not write it,
then there must be a mechanism to inform the
memory that we are interested in reading data not
writing it.
System Bus
• The computer system bus is the
method by which data is
communicated between all the
internal pieces of a computer.
There are three types of buses in
a computer
• Address Bus
• Data Bus
• Control Bus
Address Bus
• An Address Bus is a computer bus architecture used to
specify a physical address in a computer’s memory
where data is to be read or written
• It carries the addresses of the memory location the
computer’s CPU wants to read or write.
• A “16-bit” Address Bus can carry 16 bits of data at a
time, a “32-bit” Address Bus can carry 32 bits, and so
on
Address Bus (Key Points)
• Unidirectionality: The address bus is unidirectional, meaning
information is transmitted in one way only – from the CPU to the
Memory or other peripherals
• Bus Width: width determining the maximum amount of memory
that a system can handle. The “width” refers to the number of bits
that the Address Bus can carry.
• For example, a system with a 16-bit address bus can address up to
65,536 (2^16) memory locations.
• The size of the Address Bus can affect the amount of memory a CPU
can directly access. Larger Address Buses allow the CPU to address
more memory locations, means the bus can send or receive more bits
of data at the same time. This mechanics significantly speeding up
processing times.
Data Bus
• It is used to transfer the data from memory to processor in a read
operation and from processor to memory in a write operation.
• When the CPU needs to access the data stored in
memory, it sends the address associated with the data
over the address bus, whereas the actual data is
transmitted over the data bus.
Data Bus (Key points)
• The width of a data bus, measured in bits, determines
the amount of data that can be transferred
simultaneously, affecting the overall processing speed
of a computer system.
• They can be parallel or serial in nature, with parallel
buses being able to transmit multiple bits of data
simultaneously while serial buses only transmit one bit
at a time.
• Bidirectional: The data bus is Bidirectional, meaning
information is transmitted in two ways – from the CPU
to the Memory or from Memory to CPU.
Control Bus
• A Control Bus is a crucial component of a computer system
that is responsible for transmitting control signals to
coordinate actions between various system components.
• It consist of independent lines used for control purpose.
These lines are collectively known as control bus.
• It carries signals such as read, write, and interrupt requests,
enabling smooth and efficient communication among
different devices.
• For example: One line of bus is used to inform the memory
whether to do the read or write operation.
• Is control bus unidirectional or bidirectional?
System Bus
Structure -The CPU
Processor Integration
• Early computers had many separate chips for the different portions of
computer system.
Modern Microprocessors
• Modern microprocessor integrate memory-on-chip for faster access.
Microprocessor vs Microcontroller
• CPU is stand-alone, RAM, • CPU, RAM, ROM,I/O and timer
ROM,I/O and timer are separate. are on a single chip.
• General-purpose • Single-purpose.
• Mainly used in personal • Used mainly in washing
computers machines, MP3 players.
Types of Memory
Registers
• Registers are small high speed memory inside the CPU
• Quickly accessible by CPU
• It is used to store data and instructions temporarily.
• CPU contains number of registers and each register have different
functions.
• Speed can be faster if we access registers in CPU thorugh assembly
language.
• Memory cache refers to a component in a computer
system that temporarily stores frequently accessed data
to expedite the accessing process. It operates on a
smaller but faster memory type, such as SRAM, placed
between the CPU and main memory. This helps in
improving overall performance and reducing latency, as
the CPU can quickly retrieve the required data from the
memory cache instead of waiting to access it from the
slower main memory.
• There are different levels of cache memory (L1, L2, and
L3), with L1 being the fastest and closest to the
processor, while L3 is slower and farther but has a
• Web browsers: Web browsers like Google Chrome,
Mozilla Firefox, and Safari utilize memory cache to store
previously accessed websites, images, and scripts.
When you visit a website again, the browser can quickly
load the content from the cache instead of downloading
it from the internet, resulting in faster page load times
and reduced bandwidth usage.
• When the CPU needs to read or write data, it first
checks the memory cache to see if the required
information is there. If a cache hit occurs (the data is in
the cache), the CPU can access the data more quickly
than if it were stored in main memory (RAM) or
secondary storage (hard disk). If a cache miss occurs
(the data is not in the cache), the CPU fetches the data
from main memory or secondary storage and may
choose to replace some data in the cache with the new
data being accessed. Cache replacement policies, such
as Least Recently Used (LRU) or First-In, First-Out (FIFO),
can be employed to optimize this process.