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8085 Microprocessors

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Chapter_Two slide

8085 Microprocessors

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amanuel
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© © All Rights Reserved
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You are on page 1/ 35

Chapter Two

Microprocessor Architecture

1
Outline
 Features of 8085 Microprocessor & PIN Diagram 0f 8085
Microprocessor
 Address Bus & Multiplexed Address / Data Bus Control
and status signals
 Power-supply and clock frequency
 Externally initiated signals including Interrupts Serial I/O
Ports
 8085 BUS organization and 8085 registers
 Microprocessor operations: Microprocessor initiated
Operations, Internal data operations, Externally Initiated
operations
2
 Microprocessor Communication & Bus Timings De-
Introduction
 What is a Microprocessor?
 A microprocessor is nothing but!
 The Central Processing Unit of a
computer that has been constructed
on e single chip.
 It is an integrated circuit and is able
to implement all the important
functions of the CPU.
 It is built on a silicon chip and is a
clock- driven, The device is register-
based. 3
What is Microprocessor - 8085
 8085 is pronounced as "eighty-eighty-five" microprocessor.
Architecture?
 the 8085 is an 8-bit microprocessor, and it was launched by
the Intel team in the year of 1977 using NMOS(An N-channel
metal-oxide semiconductor) technology .
 Features Of 8085
 8-bit (data bus) general purpose µp
 Address bus-16 bit,
 Program counter-16-bit,
 Stack pointer-16 bit, registers 8-bit,
 Capable of addressing 64 kB of memory
 Has 40 pins as shown in fig 2
 Requires +5 v power supply
 Can operate with 3 MHz clock
4

Pin Diagram of 8085

The architecture of the 8085 microprocessor mainly includes :-


 timing & control unit,
 Arithmetic and logic unit,
 decoder,
 Instruction register,
 Interrupt control,
 a register array,
 serial input/output control.

 The most important part of the microprocessor is the central


processing unit.
5
Pin Diagram of 8085

6
Cntd…
Data Bus
 The pins from 12 to 19 are the data bus pins which are AD0 –
AD7, this carries the minimal considerable 8-bit data and
address bus.
Address Bus
 The pins from 21 to 28 are the data bus pins which are A8 –
A15, this carries the most considerable 8-bit address bus.
Status and the Control Signals
 In order to find out the behavior of the operation, these signals
are mainly considered.
 In the 8085 devices, there are 3 each the control and status
signals.
 RD – This is the signal used for the regulation of READ 7
Cntd…
 ALE: ALE corresponds to Address Latch Enable signal.
 The ALE signal is high at the time of the machine’s initial
clock cycle and this enables the last 8 bits of the address
to get latched with the memory or external latch.
 IO/M: This is the status signal that recognizes whether the
address to be allotted for I/O or for memory devices.
 READY: This pin is used to specify whether the peripheral is able
to transfer information or not.
 When this pin is high, it transfers data and if this is low, the
microprocessor device needs to wait until the pin goes to a
high state.
 S0 and S1 pins – These pins are the status signals which defines
the below operations and those are:

8
Cntd…
Clock Signals
 CLK: This is the output signal which is pin 37. This is
utilized even in other digital integrated circuits. The
frequency of the clock signal is similar to the processor
frequency.
 X1 and X2: These are the input signals at pins 1 and 2.
These pins have connections with the external oscillator
that operates the device’s internal circuitry system.
 These pins are used for the generation of the clock that
is required for the microprocessor functionality.
Reset Signals
 There are two reset pins which are Reset In and Reset Out at
9
pins 3 and 36.
Cntd…
 RESET OUT : This pin signifies that the CPU is in reset
condition.
Serial Input/Output Signals
 SID: This is the serial input data line signal. The information
that is on this dateline is taken into the 7th bit of the ACC
(Accumulator).
 SOD: This is the serial output data line signal. The ACC’s 7th
bit is the output.
Externally Initiated and Interrupts Signals
 HOLD: This pin indicates that the other device is in the need to
utilize data and address buses. This is the input pin.
 HLDA: This is the signal for HOLD acknowledgment that
signifies the received signal of HOLD request. When the request
is removed, the pin goes to a low state. 10
Cntd…
INTR : This is the interrupt request signal. It has minimal
priority when compared with other interrupt signals.
 TRAP, RST 5.5, 6.5, 7.5 These all are the input interrupt
pins.
 When any one of the interrupt pins are recognized, then the
next signal has functioned from the constant position in the
memory based on the below table:
The priority list of these interrupt signals is
 TRAP – Highest
 RST 7.5 – High
 RST 6.5 – Medium
 RST 5.5 – Low 11
Architecture of 8085 Microprocessor
8085 consists of the following blocks:

A. Register Array

B. ALU & Logical Group

C. Instruction decoder &encoder

D. Interrupt control Group

E. Serial I/O control Group

F. Timing and control circuitry


12
Cntd…
A. Register Array : It has eight addressable 8-bit register: A,
B, C, D, E, H, L, F and two 16 bit register PC and Sp.
These registers can be classified as:
i. General Purpose registers
ii.Temporary Registers
 Temporary data registers
 W and Z registers
iii.Special purpose registers:
 Accumulator
 Flag register
 Instruction register
iv.Sixteen bit registers:
 Program counter (PC)
 Stack pointer (SP) 13
Cntd…
i. General Purpose register
There are six general purpose registers in 8085
microprocessor
i.e. B. C. D. E. H. H. & L. each register can hold 8 bit
data
These registers can work in pair to hold 16 bit data
and their pairing combination is like , B-C, D-E & H-L
ii. Temporary registers
 It is an 8 bit register associated with ALU.
 It holds data during an athematic and logical operation
 It is used by the microprocessor . 14
Cntd…
iii. Special Purpose Register
Accumulator(A):
 The accumulator is an 8 bit register associated with the
ALU.
 The register “A” is an accumulator in 8085 microprocessor
 It used to hold one of the operands of arithmetic, logical and
Load/Store operation
 The final result of arithmetic or logical operation is also
placed in the accumulator
Instruction register
 The instruction register holds the opcode (operation code or
instruction code) of the is instruction which is being decoded
15
Cntd…
The five status flags of intel 8085 are:
 Carry Flag (CS)
 Parity Flag (P)
 Auxiliary Carry Flag(AC)
 Zero Flag (Z)
 Sign (S)
 Carry Flag: It is set if there is a carry or borrow from arithmetic
operation
 Parity Flag: it is set if parity is even
 It is cleared if parity is odd
Auxiliary Carry Flag: it is set if there is a carry out of bit 3
 Zero Flag: it is set if result obtained after an operation is 0
 It is set following an increment or decrement operation of that
register
16
Sign Flag: Used for indicating the sign of the data in the
Cntd…
iv. 16. Bit Register :
i. Program Counter (PC):
 It is a 16 bit special purpose register
 It used to hold the address of the memory of the next
instruction to be executed.
 It keeps the track of the instruction in the program while they
are being executed.
 The microprocessor increments the contents of the next
program counter during the execution of the instruction

ii.. Stack pointer


 It is 16 bit special function register used as memory pointer
 A stack is nothing but a portion of RAM
17
Cntd…
B. The Arithmetic and Logic Unit (ALU)
 ALU performs the arithmetic and logical operation
 The result of an operation is stored in Accumulator
C. Instruction Decoder and Machine Cycle encoder
 Decodes the op-code stored in instruction register (IR) and
establishes the sequence of the events follows.
 Encodes it and transfer to the timing and control unit to
perform the execution of the instruction.
D. Timing and Control Circuitry
Works as the brain of the CPU
For proper sequence and synchronization of all the operation
of MP,
This unit generates all the timing and control signals
18
necessary for communication between microprocessor and
Cntd…
E. Interrupt Control Group
 Interrupt:- occurrence of an external disturbance
 After servicing the interrupt, 8085 resumes its normal
working sequence
 Transfer the control to special routines
 Five interrupts:- Trap, RST7.5, RST6.5, RST5.5, INTR
 in response to INTR, it generates INTRA signal
F. Serial I/O control Group
 Data transferred on D0-D7 lines is parallel data
 But under some condition it is used serial data transfer
 Serial data is entered through SID(serial input data) and
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input (received)
8085 Bus organization
 Microprocessor preformed these operations using set of
buses: Address bus, data bus and Control bus.
 The microprocessor needs to preform the following steps:
1.Identifiy the peripherals
2.Transfer data
3. Provide timing or synchronization signals
Bus Structure in 8085
Address bus:
 microprocessor has 16bit address bus
 The CPU sends out the address of the memory
 The Address bus is unidirectional
Data Bus:
 8085 microprocessor has 8bit data bus
 Used to carry the 8 bit data
 It is Bidirectional
Control Bus: used to sending control signals to memory and I/O
20
cnt
The Address And Data Busses
 The address bus has 8 signal lines A8 – A15 which are
unidirectional.
 The other 8 address bits are multiplexed (time shared) with
the 8 data bits.
 So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7
and D0 – D7 at the same time.
 During the execution of the instruction, these lines carry the
address bits during the early part, then during the late
parts of the execution, they carry the 8 data bits.
 In order to separate the address from the data, we can use a
latch to save the value before the function of the bits
changes.
Demultiplexing AD7-AD0
 From the above description, it becomes obvious that the AD7– 21
AD0
cnt
 Also, notice that the low order bits of the address
disappear when they are needed most.
 To make sure we have the entire address for the full three
clock cycles,
 we will use an external latch to save the value of AD7– AD0
when it is carrying the address bits.
 We use the ALE signal to enable this latch.

Demultiplexing AD7-AD0
 Given that ALE operates as a pulse during T1, we will be able
to latch the address. Then when ALE goes low, the address
is saved and the AD7– AD0 lines can be used for their 22
Microprocessor Operations
 The internal logic design of the microprocessor called
its architecture, determine how and what various
operations are performed by the microprocessor
 the function of microprocessor can be classified in three
categories
1. Microprocessor initiated operation
2. Internal data operation
3. Peripheral (external initiated) operation

1. Microprocessor initiated operation


Primarily microprocessor performs four operations
a) Memory read(read data from memory)
b) Memory write (write data into memory) 23
Cntd…
2. Internal Data Operation
 The internal architecture of the 8085 microprocessor
determines how and what operation can be performed with
the data.
These operations are:-
1. Store 8 bit data
2. Performing athematic and logical operation
3. Test for conditions
4. Sequence of the execution of instructions
5. Store the data temporarily during execution in the defined R/W
memory locations called stack
To perform these operations the microprocessor
requires:-
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a)Registers
Cntd…
3. Peripherals or Externally Initiated Operation
 External devices (signals) can initiate the following operations for
which individual pins on the microprocessor chip are assigned:
Reset, Ready, Interrupt Hold.
a)Reset: when reset is activated all internal operations are
suspended and the program counter is cleared.
b)Interrupt: the microprocessor can be interrupted from normal
execution and asked to execute other instructions called “service
routine”(emergency). Microprocessor resumes its operations after
that.
c)Ready: 8085 has pin called ready, if the signal is low
microprocessor enters into wait state, this signal is used to
synchronized slower peripherals with microprocessor
25
Timing Diagram and machine cycles of 8085
Microprocessor
 Timing Diagram: Timing Diagram is a graphical
representation. It represents the execution time taken
by each instruction in a graphical format. The execution
time is represented in T-states.
 Instruction Cycle: The time required to execute an
instruction is called instruction cycle.
 Machine Cycle: The time required to access the
memory or input/output devices is called machine
cycle.
 T-State: The machine cycle and instruction cycle takes
26
Machine cycles of 8085

The 8085 microprocessor has 5 (five) basic machine


cycles.
They are:
i. Opcode fetch cycle (4T)
ii. Memory read cycle (3 T)
iii. Memory write cycle (3 T)
iv. I/O read cycle (3 T)
v. I/O write cycle (3 T)

Fig. Clock Signal 27


Cntd…
1. Signal 1.Opcode fetch machine cycle of 8085 :

Fig. Opcode fetch machine Cycle


28
Cntd…
 Each instruction of the processor has one byte opcode. The
opcodes are stored in memory. So, the processor executes the
opcode fetch machine cycle to fetch the opcode from memory.
 Hence, every instruction starts with opcode fetch machine cycle.
 The time taken by the processor to execute the opcode fetch
cycle is 4T.
 In this time, the first, 3 T-states are used for fetching the
opcode from memory and the remaining T-states are used for
internal operations by the processor.

2.Memory Read Machine Cycle of 8085: The memory


read machine cycle is executed by the processor to read a
data byte from memory. 29
Cntd…

Fig Memory Read Machine 30


3. Cycle 3. Memory Write Machine Cycle of 8085

Fig Memory Write machine cycle


 The memory write machine cycle is executed by the
processor to write a data byte in a memory location.
 The processor takes, 3T states to execute this machine
19
Cntd…
4. I/O Read Cycle of 8085
The I/O Read cycle is executed by the processor to read
a data byte from I/O port or from the peripheral,
which is I/O, mapped in the system.
The processor takes 3T states to execute this machine
cycle. The IN instruction uses this machine cycle during
the execution

32
Cntd…
Cycle 1.4.2 Timing diagram for STA 526AH

33
Cntd…
STA means Store Accumulator -The contents of the
accumulator is stored in the specified address (526A).
The opcode of the STA instruction is said to be 32H.
It is fetched from the memory 41FFH (see fig). - OF
machine cycle
Then the lower order memory address is read (6A). -
Memory Read Machine Cycle
Read the higher order memory address (52).- Memory
Read Machine Cycle
The combination of both the addresses are considered and
the content from accumulator is written in 526A. - Memory
Write Machine Cycle 34
End of chapter Two
Any question???

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