Chapter 2

Processor Structure
and Function
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 Processor Organization
• To understand the organization of the processor, let us consider
the requirements placed on the processor, the things that it
must do:
• Fetch instruction: The processor reads an instruction from
memory (register, cache, main memory).
• Interpret instruction: The instruction is decoded to determine
what action is required.
• Fetch data: The execution of an instruction may require reading
data from memory or an I/O module.
• Process data: The execution of an instruction may require
performing some arithmetic or logical operation on data.
• Write data: The results of an execution may require writing data
to memory or an I/O module.
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• To do these things, it should be clear that
the processor needs to store some data
temporarily.
• It must remember the location of the last
instruction so that it can know where to get
the next instruction. It needs to store
instructions and data temporarily while an
instruction is being executed. In other
words, the processor needs a small internal
memory.
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The Figure below is a simplified view of a processor, indicating its
connection to the rest of the system via the system bus. A similar
interface would be needed for any of the interconnection structures of
the system.

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• You will recall that the major components of the
processor are an arithmetic and logic unit
(ALU) ,control unit (CU) and register .The ALU
does the actual computation or processing of
data.
• The control unit controls the movement of data
and instructions into and out of the processor
and controls the operation of the ALU.

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• The figure below shows a more detailed view of the
processor. The data transfer and logic control paths are
indicated, including an element labeled internal
processor bus.
• This element is needed to transfer data between the
various registers and the ALU because the ALU in fact
operates only on data in the internal processor memory.
• The figure also shows typical basic elements of the ALU.
Note the similarity between the internal structure of the
computer as a whole and the internal structure of the
processor. In both cases, there is a small collection of
major elements(computer: processor, I/O, memory,
Inter Connection Buss; processor: control unit, ALU,
registers) connected by data paths.
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Internal Structure of the CPU

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 Register Organization
• Within the processor, there is a set of registers that
function as a level of memory above main memory
and cache in the hierarchy. The registers in the
processor perform two roles:
• User-visible registers: Enable the machine- or assembly
language programmer to minimize main memory references
by optimizing use of registers.
• Can be accesses via assembly instructions
• Part of computer architecture

• Control and status registers: Used by the control unit to

control the operation of the processor and by privileged,
operating system programs to control the execution of
programs. 8
• Cannot (in general) be accessed via assembly
instructions
—Part of computer organization
—Used by:
–control unit
–OS

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 User-Visible Registers
• A user-visible register is one that may be
referenced by means of the machine language
that the processor executes. We can characterize
these in the following categories:
• General purpose register
• Data register
• Address register
• Condition codes register

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• General-purpose registers can be assigned to a variety
of functions by the programmer. Any general-purpose
register can contain the operand for any opcode.
• They used to handle floating-point and stack
operations.
• General-purpose registers can be used for addressing
functions (register indirect, displacement)
• Data registers may be used only to hold data and
cannot be employed in the calculation of an operand
address.
• Address registers devoted to a particular addressing
mode.

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 Types of Address Registers
• Segment pointers: a segment register holds the
address of the base of the segment. There may
be multiple registers: for example, one for the
operating system and one for the current
process.
• Index registers: These are used for indexed
addressing and may be auto indexed.
• Stack pointer: a dedicated register that points to
the top of the stack.

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 Design Issues of Registers
• Whether to use completely general-purpose registers or to
specialize purpose
• The number of registers, either general purpose or data plus
address, to be provided.
– this affects instruction set design because more registers
require more operand specifies bits.
– Fewer registers result in more memory references.
– more registers do not reduce memory references.
• Register length
– Registers that must hold addresses obviously must be at least
long enough to hold the largest address. Data registers should
be able to hold values of most data types. Some machines
allow two contiguous registers to be used as one for holding
double-length values.
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• Registers that must hold addresses obviously must
be at least long enough to hold the largest
address.
• Data registers should be able to hold values of
most data types.
• Condition Codes: are bits set by the processor hardware
as the result of operations. An arithmetic operation may
produce a positive, negative, zero, or overflow result.
• Condition code bits are collected into one or more
registers. Usually, they form part of a control register.
Generally, machine instructions allow these bits to be
read by implicit reference, but the programmer cannot
alter them.
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 • Advantages of Condition Codes
1. Because condition codes are set by normal arithmetic
and data movement instructions, they should reduce
the number of COMPARE and TEST instructions needed.
2. Conditional instructions, such as BRANCH are simplified
relative to composite instructions, such as TEST AND
BRANCH.
3. Condition codes facilitate multiway branches.For
example, a TEST instruction can be followed by two
branches, one on less than or equal to zero and one on
greater than zero.

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 Disadvantages of Condition Codes
1. Condition codes add complexity, both to the hardware
and software.Condition code bits are often modified in
different ways by different instructions, making life
more difficult for both the micro programmer and
compiler writer.
2. Condition codes are irregular; they are typically not
part of the main data path, so they require extra
hardware connections.
3. Often condition code machines must add special non-
condition-code instructions for special situations
anyway, such as bit checking, loop control, and atomic
semaphore operations.
4. In a pipelined implementation, condition codes require
special synchronization to avoid conflicts. 16
 Control and Status Registers
• Processor registers that are employed to
control the operation of the processor.
• They are not visible to the user. Some of them
may be visible to machine instructions
executed in a control or operating system
mode.

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 • Four types of registers are essential to instruction
execution:
• Program counter (PC): Contains the address of an
instruction to be fetched
• Instruction register (IR): Contains the instruction
most recently fetched
• Memory address register (MAR): Contains the
address of a location in memory
• Memory buffer register (MBR): Contains a word
of data to be written to memory or the word
most recently read
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The (Program Status Word Register)PSW
typically contains condition codes plus other status
information. Common fields or flags include the
following: The PSW typically contains condition codes
plus other status information. Common fields or flags
include the following:
• Sign : Contains the sign bit of the result of the last
arithmetic operation.
• Zero: Set when the result is 0.
• Carry: Set if an operation resulted in a carry (addition)
into or borrow (subtraction) out of a high-order bit. Used
for multiword arithmetic operations.

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• Equal: Set if a logical compare result is equality.
• Overflow: Used to indicate arithmetic overflow.
• Interrupt enable/disable: Used to enable or
disable interrupts
• Supervisor: Indicates whether the processor is
executing in supervisor or user mode. Certain
privileged instructions can be executed only in
supervisor mode, and certain areas of memory
can be accessed only in supervisor mode

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 Instruction cycle
An instruction cycle includes the following stages:
• Fetch: Read the next instruction from memory
into the processor.
• Execute: Interpret the opcode and perform the
indicated operation.
• Interrupt: If interrupts are enabled and an
interrupt has occurred, save the current process
state and service the interrupt.

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• Fetching of indirect addresses as one more
instruction stages. The result is shown in the
Figure above. The main line of activity consists of
alternating instruction fetch and instruction
execution activities. After an instruction is
fetched, it is examined to determine if any
indirect addressing is involved. If so, the required
operands are fetched using indirect addressing.
Following execution, an interrupt may be
processed before the next instruction fetch.

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23
 Data Flow
• The exact sequence of events during an instruction cycle
depends on the design of the processor. Let us assume
that a processor that employs a memory address register
(MAR), a memory buffer register (MBR), a program
counter (PC), and an instruction register (IR).
• During the fetch cycle, an instruction is read from
memory. The Figure below shows the flow of data during
this cycle. The PC contains the address of the next
instruction to be fetched. This address is moved to the
MAR and placed on the address bus. The control unit
requests a memory read, and the result is placed on the
data bus and copied into the MBR and then moved to
the IR. Meanwhile, the PC is incremented by 1,
preparatory for the next fetch. 24
Data Flow, Fetch Cycle

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• The execute cycle takes many forms; the form depends
on which of the various machine instructions is in the IR.
This cycle may involve transferring data among registers,
read or write from memory or I/O, and/or the invocation
of the ALU.
• The interrupt cycle, the current contents of the PC must
be saved so that the processor can resume normal
activity after the interrupt. Thus, the contents of the PC
are transferred to the MBR to be written into memory.
The special memory location reserved for this purpose is
loaded into the MAR from the control unit. It might be a
stack pointer. The PC is loaded with the address of the
interrupt routine. As a result, the next instruction cycle
will begin by fetching the appropriate instruction.
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Data Flow, Interrupt Cycle

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 Instruction Pipelining
• Introduction, As computer systems evolve, greater
performance can be achieved by taking advantage of
improvements in technology, such as faster circuitry. In
addition, organizational enhancements to the processor
can improve performance. We have already seen some
examples of this, such as the use of multiple registers
rather than a single accumulator, and the use of a cache
memory.
• What is Instruction pipelining?

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• Instruction pipelining is similar to the use of an
assembly line in a manufacturing plant. An assembly line
takes advantage of the fact that a product goes through
various stages of production. By laying the production
process out in an assembly line, products at various
stages can be worked on simultaneously. This process is
also referred to as pipelining, because, as in a pipeline,
new inputs are accepted at one end before previously
accepted inputs appear as outputs at the other end.
• Instruction processing divided in to two stages:
– fetch instruction and
– execute instruction.

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 There are times during the execution of an instruction when
main memory is not being accessed. This time could be used to
fetch the next instruction in parallel with the execution of the
current one. Below Figure (a) depicts this approach. The
pipeline has two independent stages. The first stage fetches an
instruction and buffers it. When the second stage is free, the
first stage passes it the buffered instruction. While the second
stage is executing the instruction, the first stage takes advantage
of any unused memory cycles to fetch and buffer the next
instruction. This is called instruction prefetch or fetch overlap.
• Note that this approach, which involves instruction buffering,
requires more registers. In general, pipelining requires registers
to store data between stages. It should be clear that this
process will speed up instruction. It should be clear that this
process will speed up instruction execution. If the fetch and
execute stages were of equal duration, the instruction cycle
time would be halved. 30
Two-Stage Instruction Pipeline

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Instruction Cycle State Diagram

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• Fetch Instruction (FI): Read the next expected instruction
into a buffer.
• Decode Instruction (DI): Determine the opcode and the
operand specifies.
• Calculate Operands (CO): Calculate the effective address
of each source operand. This may involve displacement,
register indirect, indirect, or other forms of address
calculation.
• Fetch Operands (FO): Fetch each operand from memory.
Operands in registers need not be fetched.
• Execute Instruction (EI): Perform the indicated operation
and store the result, if any, in the specified destination
operand location.
• Write Operand (WO): Store the result in memory. 33
Timing of Pipeline

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 Summary
◆A processor includes both user-visible registers and
control/status registers. The former may be referenced,
implicitly or explicitly, in machine instructions. User-
visible registers may be general purpose or have a special
use, such as fixed-point or floating-point numbers,
addresses, indexes, and segment pointers. Control and
status registers are used to control the operation of the
processor. One obvious example is the program counter.
Another important example is a program status word
(PSW) that contains a variety of status and condition bits.
These include bits to reflect the result of the most recent
arithmetic operation, interrupt enable bits, and an
indicator of whether the processor is executing in
supervisor or user mode. 35
 Summary
◆ Processors make use of instruction pipelining to speed
up execution. In essence, pipelining involves breaking
up the instruction cycle into a number of separate
stages that occur in sequence, such as fetch
instruction, decode instruction, determine operand
addresses, fetch operands, execute instruction, and
write operand result. Instructions move through these
stages, as on an assembly line, so that in principle,
each stage can be working on a different instruction at
the same time. The occurrence of branches and
dependencies between instructions complicates the
design and use of pipelines.

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