Combinational Logic Design

COE 202
Digital Logic Design
Dr. Aiman El-Maleh
College of Computer Sciences and Engineering
King Fahd University of Petroleum and Minerals
 Outline
 Combinational Logic Circuits
 Combinational Circuits Design Procedure
 Design Examples
 BCD to Excess 3 Code Converter
 BCD to 7-Segment Decoder for LED
 Y=X2
 Y=|3X-1|

Combinational Logic Design COE 202– Digital Logic Design – KFUPM

slide 2
 Combinational Logic Circuits
 A combinational logic circuit has:
 A set of m Boolean inputs,
 A set of n Boolean outputs, and
 n logic functions, each mapping the 2m input
combinations to an output
 Outputs are determined only by present inputs

Each Output = F (the m inputs)

Combinational Logic Design COE 202– Digital Logic Design – KFUPM

slide 3
 Combinational Circuits Design
Procedure
 1. Specification (Requirement)
 Write a specification for what the circuit should do e.g. add two
4-bit binary numbers
 Specify names for the inputs and outputs
 2. Formulation
 Convert the Specification into a form that can be Optimized
 Usually as a truth table or a set of Boolean equations that define
the required relationships between the inputs and outputs
 3. Logic Optimization
 Apply logic optimization (2-level & multi-level) to minimize the
logic circuit
 Provide a logic diagram or a netlist for the resulting circuit using
ANDs, ORs, and inverters
Combinational Logic Design COE 202– Digital Logic Design – KFUPM
slide 4
 Combinational Circuits Design
Procedure
 4. Technology Mapping and Design Optimization
 Map the logic diagram or netlist to the implementation
technology and gate type selected, e.g. CMOS NANDs
 Perform design optimizations of gate costs, gate delays, fan-
outs, power consumption, etc.
 Sometimes this stage is merged with stage 3
 5. Verification
 Verify that the final design satisfies the original specification-
Two methods:
 Manual: Ensure that the truth table for the final technology-mapped
circuit is identical to the truth table derived from specifications
 By Simulation: Simulate the final technology-mapped circuit on a
CAD tool and test it to verify that it gives the desired outputs at the
specified inputs and meets delay specs etc.
Combinational Logic Design COE 202– Digital Logic Design – KFUPM
slide 5
 BCD to Excess 3 Code Converter
 1. Specification
 Transforms BCD code for the decimal
digits (0-9) to the corresponding
Excess-3 code
 BCD code words for digits 0 through 9:
4-bit patterns 0000 to 1001, respectively
 Excess-3 code words for digits 0 through
9: 4-bit patterns obtained by adding 3
(binary 0011) to each BCD code input
 2. Formulation
 In the form of a truth table: Variables
 BCD: A,B,C,D Excess-3: W,X,Y,Z
 Don’t Cares: BCD 1010 to 1111

Combinational Logic Design COE 202– Digital Logic Design – KFUPM

slide 6
 BCD to Excess 3 Code Converter
3. Logic Minimization using K-maps

Minimal Sum-of-Product expressions:

, , ,
Additional 3-Level Optimizations: extract common term
T1=, ,
Combinational Logic Design COE 202– Digital Logic Design – KFUPM
slide 7
 BCD to Excess 3 Code Converter
4. Technology Mapping
Draw a logic diagram using ANDs, ORs, and inverters
Other gates can be used, such as NAND, NOR, and XOR

a w Using XOR gates

x
b a w
c
b x
y
d c y
z d z
Combinational Logic Design COE 202– Digital Logic Design – KFUPM
slide 8
 BCD to Excess 3 Code Converter
5. Verification Truth Table of the
Can be done manually Circuit Diagram

Extract output functions from circuit diagram

Find the truth table of the circuit diagram
Match it against the specification truth table
Verification process can be automated
Using a simulator for complex designs
a w = a + b(c + d)
b
x = b  (c + d)
c y = c  d'
d z = d'
Combinational Logic Design COE 202– Digital Logic Design – KFUPM
slide 9
 BCD to Excess 3 Code Converter
 Run the simulation of the circuit
INPUTS
A
B
C
D
OUTPUTS
W
X
Y
Z

 Do the
0
simulation output 50 ns
combinations 100 ns
match the original
specification truth table?

Combinational Logic Design COE 202– Digital Logic Design – KFUPM

slide 10
 BCD to 7-Segment Decoder for
LED
 1. Specification
 Transforms a BCD input code for the decimal digits (0 to 9) to 7
outputs (one for each of the seven LED segments) used to drive
the display
 Each output indicates whether the corresponding segment is
ON (1) or OFF (0) for the input BCD code

Combinational Logic Design COE 202– Digital Logic Design – KFUPM

slide 11
 BCD to 7-Segment Decoder for
LED
 2. Formulation
 4 Input Variables
 BCD: A,B,C,D (LSB)
 7 Output Variables
 Drivers for the 7 Segments:
a,b,c,d,e,f,g
 (1 = segment lit,
i.e. active high)
 Don’t Cares
 None!
Display is OFF for
non BCD codes

Combinational Logic Design COE 202– Digital Logic Design – KFUPM

slide 12
 BCD to 7-Segment Decoder for
LED
3. Logic Minimization Using K-Maps
𝐶𝐷 K-map for 𝐶𝐷 K-map for 𝐶𝐷 K-map for
𝐴𝐵 00 01 11 10 𝐴𝐵 00 01 11 10 𝐴𝐵 00 01 11 10
00 1 1 1 00 1 1 1 1 00 1 1 1
01 1 1 1 01 1 1 01 1 1 1 1
11 11 11
10 1 1 10 1 1 10 1 1

Optimized Logic Expressions

Extracting common terms

Let are shared gates
Combinational Logic Design COE 202– Digital Logic Design – KFUPM
slide 13
 BCD to 7-Segment Decoder for
LED
3. Logic Minimization Using K-Maps

Common AND Terms Optimized Logic Expressions

 Shared Gates

Combinational Logic Design COE 202– Digital Logic Design – KFUPM

slide 14
 Design Example: Y=X2
 Given a 3-bit unsigned number X, design a circuit to
compute the equation Y=X2
 First, we need to determine the number of bits needed at
the output
 Since the maximum value at X=7, then X2=49. Thus, we need 6
bits to represent the correct output
 Next, we derive the truth table having 3 inputs and 6
outputs
 After that we need to derive optimized output equations
for each output
 Before using kmap, we check if an output equation can be
deduced if it is either constant or it is equal to an input variable
or its complement
Combinational Logic Design COE 202– Digital Logic Design – KFUPM
slide 15
 Design Example: Y=X2
Truth Table The following output
X2 X1 X0 Y5 Y4 Y3 Y2 Y1 Equations can be derived
Y0 From the truth table:
0 0 0 0 0 0 0 0 0
Y0 = X0
0 0 1 0 0 0 0 0 1
Y1 = 0
0 1 0 0 0 0 1 0 0
Y2 = X1 X0’
0 1 1 0 0 1 0 0 1
Y5 = X2 X1
1 0 0 0 1 0 0 0 0
1 0 1 0 1 1 0 0 1
The remaining output
1 1 0 1 0 0 1 0 0
Equations can be derived
1 1 1 1 1 0 0 0 1
Using 3-var Kmaps

Combinational Logic Design COE 202– Digital Logic Design – KFUPM

slide 16
 Design Example: Y=|3X-1|
 Given a 3-bit unsigned number X, design a circuit to
compute the equation Y=|3X-1|
 Since the maximum value at X=7, then Y=|3*7-1|=20.
Thus, we need 5 bits to represent the correct output
X2 X1 X0 Y4 Y3 Y2 Y1 Y0
The following output
0 0 0 0 0 0 0 1
0 0 1 0 0 0 1 0
Equations can be derived
0 1 0 0 0 1 0 1 From the truth table:
0 1 1 0 1 0 0 0 Y0 = X0’
1 0 0 0 1 0 1 1 Y4 = X2 X1
1 0 1 0 1 1 1 0
1 1 0 1 0 0 0 1
1 1 1 1 0 1 0 0

Combinational Logic Design COE 202– Digital Logic Design – KFUPM

slide 17