boolean_algebra
boolean_algebra
(x + y)(x + y′)
= x + xy + xy′ + yy′
= x(1 + y + y′)
=x
xy + x′z + yz
= xy + x′z + yz(x + x′)
= xy + x′z + xyz + x′yz
= xy(1 + z) + x′z(1 + y)
= xy + x′z
Q. Prove that: (x + y)(x̅ + y) = y
Q. Prove the Boolean expression: AB + AB′C + A′BC = AB + AC + BC
Q. Minimize the expression: AB + AC̅ + BC using theorem and properties
of Boolean Algebra.
Q. Simplify the given Boolean expression
AB’C+A’B’C+ABC
AB+A’BC+BC
PQ’+Q(P+Q)+P(P’+Q)
(X+Y)(XY’Z+XYZ+XY’Z’)
Complement of a function
The complement of a function F is F′ and is obtained from an interchange of
0’s for 1’s and1’s for 0’s in the value of F. The complement of a function
may be derived algebraically through De Morgan’s theorem.
For each specific implementation technology, there are details that differ
in their electronic circuit design and circuit parameters. The most
important parameters used to characterize an implementation technology
are:
Fan-in
For high-speed technologies, fan-in, the number of inputs to a gate, is
often restricted on gate primitives to no more than four or five. This is
primarily due to electronic considerations related to gate speed. To build
gates with larger fan-in, interconnected gates with lower fan-in are used
during technology mapping.
Characteristics of digital logic families (Technology Parameters)
Propagation delay:
The signals through a gate take a certain amount of time to propagate
from the inputs to the output. This interval of time is defined as the
propagation delay of the gate. This is symbolized as tpd. Propagation
delay is measured in nanoseconds (ns). 1 ns is equal to 10-9 of a second.
The signals that travel from the inputs of a digital circuit to its outputs
pass through a series of gates. The sum of the propagation delays
through the gates is the total delay of the circuit.
Characteristics of digital logic families (Technology Parameters)
In fig, VOL is the maximum voltage that the output can be when in the low-
level state. The circuit can tolerate any noise signal that is less than the
noise margin (VIL - VOL ) because the input will recognize the signal as
being in the low-level state. Any signal greater than V OL plus the noise-
margin figure will send the input voltage into the indeterminate range,
which may cause an error in the output of the gate. In a similar fashion, a
negative-voltage noise greater than V OH - VIH will send the input voltage
into the indeterminate range.
The parameters for the noise margin in a standard TTL NAND gate are V OH
= 2.4 V, VOL = 0.4 V, VIH = 2 V, and VIL = 0.8 V. The high-state noise
margin is 2.4 - 2 = 0.4 V, and the low-state noise margin is 0.8 - 0.4 = 0.4 V.
Positive Logic and Negative logic
In the binary system, the digits 1 and 0 are called binary digits. To
represent these two bits, we use two different voltage levels. These
voltages are called logic levels.
Generally higher voltage HIGH represents 1 and low voltage LOW
represents 0. This is called positive logic. Another system that represents
1 with LOW and 0 with HIGH is called negative logic. In a practical
digital circuit, however HIGH and LOW can be any voltage between a
specified minimum and maximum voltages.
Comparison