Semiconductor Main

Memory
SEMICONDUCTOR MAIN
MEMORY
• In earlier computers, the most common form of random-access
storage for computer main memory employed an array of doughnut-
shaped ferromagnetic loops referred to as cores. Hence, main
memory was often referred to as core, a term that persists to this day.
The advent of, and advantages of, microelectronics has long since
vanquished the magnetic core memory
Organization
• The basic element of a semiconductor memory is the memory cell.
Although a variety of electronic technologies are used, all
semiconductor memory cells share certain properties:
• They exhibit two stable (or semi stable) states, which can be used to
represent binary 1 and 0.
• They are capable of being written into (at least once), to set the state.
• They are capable of being read to sense the state.
Memory Cell Operation
• Most commonly, the cell has three functional terminals capable of
carrying an electrical signal.
• The select terminal, as the name suggests, selects a memory cell for a
read or write operation.
• The control terminal indicates read or write.
• For writing, the other terminal provides an electrical signal that sets
the state of the cell to 1 or 0.
• For reading, that terminal is used for
output of the cell’s state.
DRAM and SRAM
 DYNAMIC RAM
• RAM technology is divided into two technologies: dynamic and static.
• A dynamic RAM (DRAM) is made with cells that store data as charge on capacitors. The presence
or absence of charge in a capacitor is interpreted as a binary 1 or 0.
Because capacitors have a natural tendency to discharge, dynamic RAMs require periodic charge
refreshing to maintain data storage. The term
dynamic refers to this tendency of the stored charge to leak away, even with power
continuously applied.
• Figure is a typical DRAM structure for an individual cell that stores 1 bit.
• The address line is activated when the bit value from this cell is to be read or written.
The transistor acts as a switch that is closed (allowing current to flow) if a voltage
is applied to the address line and open (no current flows) if no voltage is present
on the address line.
• For the write operation, a voltage signal is applied to the bit line; a high voltage
represents 1, and a low voltage represents 0. A signal is then applied to the address
line, allowing a charge to be transferred to the capacitor.
• For the read operation, when the address line is selected, the transistor turns
on and the charge stored on the capacitor is fed out onto a bit line and to a sense
amplifier. The sense amplifier compares the capacitor voltage to a reference value
and determines if the cell contains a logic 1 or a logic 0. The readout from the cell
STATIC RAM
• In contrast, a static RAM (SRAM) is a digital device that uses the
same logic elements used in the processor. In a SRAM, binary values are stored
using traditional flip-flop logic-gate configurations. A static RAM will hold its data as long as power is supplied to it.
• Figure is a typical SRAM structure for an individual cell.
• Four transistors (T1,T2,T3,T4) are cross connected in an arrangement that produces a stable logic state.
• In logic state 1, point C1 is high and point C2 is low; in this state,T1 and T4 are off and T2
and T3 are on.1
• In logic state 0, point C1 is low and point C2 is high; in this state,T1 and
T4 are on and T2 and T3 are off. Both states are stable as long as the direct current (dc)
voltage is applied.
Unlike the DRAM, no refresh is needed to retain data.
• As in the DRAM, the SRAM address line is used to open or close a switch.
• The address line controls two transistors (T5 and T6).When a signal is applied to this
line, the two transistors are switched on, allowing a read or write operation.
For a write operation, the desired bit value is applied to line B, while its complement is applied
to line . This forces the four transistors (T1, T2, T3, T4) into the proper state.
• For a read operation, the bit value is read from line B.
SRAM VERSUS DRAM
• Both static and dynamic RAMs are volatile; that is, power must be continuously
supplied to the memory to preserve the bit values.
• A dynamic memory cell is simpler and smaller than a static memory cell. Thus, a
DRAM is more dense (smaller cells= more cells per unit area) and less expensive
than a corresponding SRAM.
• On the other hand, a DRAM requires the supporting refresh circuitry.
• For larger memories, the fixed cost of the refresh circuitry is more than
compensated for by the smaller variable cost of DRAM cells.
• Thus, DRAMs tend to be favored for large memory requirements. A final point is
that SRAMs are generally somewhat faster than DRAMs. Because of these relative
characteristics, SRAM is used for cache memory (both on and off chip), and DRAM
is used for main memory.
Types of ROM
• As the name suggests, a read-only memory (ROM) contains a
permanent pattern of data that cannot be changed. A ROM is
nonvolatile; that is, no power source is required to maintain the bit
values in memory. While it is possible to read a ROM, it is not possible
to write new data into it. Other potential applications include
• Library subroutines for frequently wanted functions
• System programs
• Function tables
• A ROM is created like any other integrated circuit chip, with the data
actually wired into the chip as part of the fabrication process. This
presents two problems:
• The data insertion step includes a relatively large fixed cost, whether
one or thousands of copies of a particular ROM are fabricated.
• There is no room for error. If one bit is wrong, the whole batch of
ROMs must be thrown out.
Types of ROM
• Programmable ROM (PROM)
• Erasable Programmable read-only memory (EPROM)
• Electrically Erasable Programmable read-only memory (EEPROM)
• Flash memory
Programmable ROM (PROM)
• PROM is nonvolatile and may be written into only once. For the
PROM, the writing process is performed electrically and may be
performed by a supplier or customer at a time later than the original
chip fabrication. Special equipment is required for the writing or
“programming” process. PROMs provide flexibility and convenience.
The ROM remains attractive for high-volume production runs.
• Another variation on read-only memory is the read-mostly memory,
which is useful for applications in which read operations are far more
frequent than write operations but for which nonvolatile storage is
required. There are three common forms of read-mostly memory:
EPROM, EEPROM, and flash memory.
Erasable Programmable Read-
Only Memory EPROM
• The optically erasable programmable read-only memory (EPROM) is read
and written electrically, as with PROM. However, before a write operation, all
the storage cells must be erased to the same initial state by exposure of the
packaged chip to ultraviolet radiation. Erasure is performed by shining an
intense ultraviolet light through a window that is designed into the memory
chip. This erasure process can be performed repeatedly; each erasure can
take as much as 20 minutes to perform.
• Thus, the EPROM can be altered multiple times and, like the ROM and PROM,
holds its data virtually indefinitely. For comparable amounts of storage, the
• EPROM is more expensive than PROM, but it has the advantage of the
multiple update capability.
Flash Memory
• Another form of semiconductor memory is flash memory (so named
because of the speed with which it can be reprogrammed). First introduced
in the mid-1980s, flash memory is intermediate between EPROM and
EEPROM in both cost and functionality. Like EEPROM, flash memory uses an
electrical erasing technology.
• An entire flash memory can be erased in one or a few seconds, which is
much faster than EPROM. In addition, it is possible to erase just blocks of
memory rather than an entire chip. Flash memory gets its name because the
microchip is organized so that a section of memory cells are erased in a
single action or “flash.” However, flash memory does not provide byte-level
erasure. Like EPROM, flash memory uses only one transistor per bit, and so
achieves the high density (compared with EEPROM) of EPROM.
Electrically Erasable Programmable
Read-only Memory (EEPROM)
• A more attractive form of read-mostly memory is electrically erasable
programmable read-only memory (EEPROM). This is a read-mostly
memory that can be written into at any time without erasing prior
contents; only the byte or bytes addressed are updated. The write
operation takes considerably longer than the read operation, on the
order of several hundred microseconds per byte. The EEPROM
combines the advantage of non-volatility with the flexibility of being
updatable in place, using ordinary bus control, address, and data
lines. EEPROM is more expensive than EPROM and also is less dense,
supporting fewer bits per chip.
Synchronous DRAM
• SDRAM exchanges data with the processor synchronized to an external clock
signal and running at the full speed of the processor/memory bus without
imposing wait states.
In a typical DRAM, the processor presents With synchronous access, the DRAM
addresses and control levels to the moves data in and out under control of
memory, indicating that a set of data at a the system clock. The processor or other
particular location in memory should be master, issues the instruction and
either read from or written into the address information, which is latched by
DRAM. After a delay, the access time, the the DRAM. The DRAM then responds
DRAM either writes or reads the data. after a set number of clock cycles.
During the access-time delay, the DRAM Meanwhile, the master can safely do
performs various internal functions, such other tasks while the SDRAM is
as activating the high capacitance of the processing the request.
row and column lines, sensing the data,
and routing the data out through the
output buffers. The processor must
simply wait through this delay, slowing
system performance.
Mode Register
• The mode register specifies the burst length, which is the number of
separate units of data synchronously fed onto the bus. The register also
allows the programmer to adjust the latency between receipt of a read
request and the beginning of data transfer.
• In this case, the burst length is 4
and the latency is 2.
The burst read command is initiated
by having CS(chip select) and
CAS(column address strobe) low while
RAS(row address strobe) and WE(write enable) high at rising edge of clock.
Rambus DRAM
• Rambus DRAM (RDRAM), and its successors Concurrent Rambus
DRAM (CRDRAM) and Direct Rambus DRAM (DRDRAM), are types of
synchronous dynamic random-access memory (SDRAM) developed by
Rambus from the 1990s through to the early 2000s. The third-generation of
Rambus DRAM, DRDRAM was replaced by XDR DRAM. Rambus DRAM was
developed for high-bandwidth applications and was positioned by Rambus as
replacement for various types of contemporary memories, such as SDRAM.
• RDRAM chips are vertical packages, with all pins on one side. The chip
exchanges data with the processor over 28 wires no more than 12
centimeters long.
• The bus can address up to 320 RDRAM chips and is rated at 1.6 GBps.
• The special RDRAM bus delivers address and control information
using an asynchronous block-oriented protocol. After an initial 480 ns
access time, this produces the 1.6 GBps data rate. What makes this
speed possible is the bus itself, which defines impedances, clocking,
and signals very precisely. Rather than being controlled by the explicit
RAS, CAS, R/W, and CE signals used in conventional DRAMs, an
RDRAM gets a memory request over the high-speed bus. This request
contains the desired address, the type of operation, and the number
of bytes in the operation
DDR SDRAM
• SDRAM is limited by the fact that it can only send data to the
processor once per bus clock cycle.
• A new version of SDRAM, referred to as double-data-rate SDRAM can
send data twice per clock cycle, once on the rising edge of the clock
pulse and once on the falling edge. DDR DRAM was developed by the
JEDEC Solid State Technology Association, the Electronic Industries
Alliance’s semiconductor-engineering-standardization body.
Numerous companies make DDR chips, which are widely used in
desktop computers and servers.
DDR Read/Write
• The data transfer is synchronized to
both the rising and falling edge of
the clock. It is also synchronized to a
bidirectional data strobe (DQS)
signal that is provided by the
memory controller during a
read and by the DRAM during a
write.
• There have been two generations of improvement to the DDR technology.
• DDR2 increases the data transfer rate by increasing the operational
frequency of the RAM chip and by increasing the pre-fetch buffer from 2
bits to 4 bits per chip. The pre-fetch buffer is a memory cache located on
the RAM chip. The buffer enables the RAM chip to preposition bits to be
placed on the data base as rapidly as possible.
• DDR3, introduced in 2007, increases the pre-fetch buffer size to 8 bits.
• Theoretically, a DDR module can transfer data at a clock rate in the range of
200 to 600 MHz; a DDR2 module transfers at a clock rate of 400 to 1066
MHz; and a DDR3 module transfers at a clock rate of 800 to 1600 MHz. In
practice, somewhat smaller rates are achieved.
Cache DRAM

• Cache DRAM (CDRAM), developed by Mitsubishi [HIDA90, ZHAN01],

integrates a small SRAM cache (16 Kb) onto a generic DRAM chip.
• The SRAM on the CDRAM can be used in two ways. First, it can be used
as a true cache, consisting of a number of 64-bit lines. The cache mode
of the CDRAM is effective for ordinary random access to memory.
• The SRAM on the CDRAM can also be used as a buffer to support the
serial access of a block of data. For example, to refresh a bit-mapped
screen, the CDRAM can pre-fetch the data from the DRAM into the
SRAM buffer. Subsequent accesses to the chip result in accesses solely
to the SRAM.