Session 4

Behavioural Modeling

Session Speaker :
Vasudeva Murthy T

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 Session Objectives

• To understand the importance and advantages of

behavioural modeling
• To learn about the different data types of the language
• To understand the concept of procedural blocks
• To learn the functioning of procedural assignment
statements
• To comprehend the various conditional assignment
statements
• To learn about Pragmas and their relevance to designers
• To learn about various forms of loops and their
capabilities

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 Session Topics

• Disadvantages of structural modeling

• Data types in VERILOG
• Initial and Always blocks
• Procedural blocks and their sensitivity lists
• Timing control operators
• Conditional assignment statements and hardware inference
• Pragmas / synthesis directives
• Looping assignment statements

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 Drawbacks of Structural Modeling
• Structural modeling is the most efficient method of
modeling but has the following disadvantages
– This kind of modeling can get tedious for very large designs
– Always architecture / hardware of problem being solved may
not be known
– Arriving at structure first and then modeling it will take lots of
time
– Building edge triggered circuits with structural modeling alone
can be very tricky
• Though being ideally the best way to model a hardware
time-to-market issues and complexity involved works
against it

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 Need for behavioural modeling

• Present day problems are quite complex and so are the

solutions
• Functionality required is known but not hardware
• Behaviour of system can be very easily explained in higher
level abstraction
• Represents both concurrent and sequential behaviour of
hardware
• Repetitive task can be expressed only once and then called
many number of times

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 Behavioral Coding Style
Most advanced coding style:
flexible and high-level closest to programming languages
allows use of conditional statements, loops, case etc.
Best for verification, but by no means ideal...
• Behavior: Actions a circuit is supposed to perform when it is active.
• Algorithmic description: Need “ variables ” similar to PLs!

Abstraction of data storage elements - register objects:

• reg R one bit register - default value x before first assignment
• time T can store/manipulate simulation time
• integer N by default at least 32 bit - stores values signed
• real R default value is 0

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 Data Types
There are basically two kinds of data types in Verilog
• Nets
– Represent interconnects / physical connection from one point to
other
– Primarily used only in dataflow and structural modeling
– Structural modeling and dataflow modeling can use only nets
– Must be driven by a driver, such as a gate or continuous
assignment statement
– Default value is high impedance
– Examples
• wire, wand, wor
• tri, traind, trior
• supply0, supply1
• Registers
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 Registers
• Analogous to the concept of storage / holds some value
• Primarily used only in behavioural modeling
• There are various kinds
– reg // stores a value, can be single bit or vector
– integer // used in computations, is of 32 bits
– time // used to see the simulation time
– real // used to store real numbers, uses 64 bits
– realtime // stores time as real numbers
• Need not necessarily result in flip-flop/ latch
• Default value is ‘x’
• Cannot be driven by a gate

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 Signed vs Unsigned
Net types and reg variables unsigned by default
– Have to declare them as signed if desired!
reg signed [7:0] signedreg;
wire signed [3:0] signedwire;
All bit-selects and part-selects are unsigned
– A[6], B[5:2], etc.
integer, real, realtime are signed
System calls can force values to be signed or unsigned
reg [5:0] A = $unsigned(-4);
reg signed [5:0] B = $signed(4’b1101);

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 Ports and Data Types

Input Port Output Port

net/register net net/register net

net
Inout Port

net

• Input: Externally can be connected to register/net but internally can

be connected only to a net
• Output: Can be driven from a register/net but can drive only a net
• Inout : Can be connected only to nets both externally and internally
i.e. can be driven by nets and can drive only nets

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 Behavioural Modeling
• Uses procedural blocks which are of two types
– initial
– always
• Contains set of statements which execute sequentially
• Can have more than one procedural blocks
• All procedural blocks work in parallel / concurrent in
nature
• Updates variables of data type register
• They can not be nested

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 Procedural Blocks
initial :
– Used primarily to initialize variables
– Executes only once, initially at time 0
– More than one statement in a block needs to be grouped with ‘begin’
& ‘end’
– Will not synthesize into hardware
– Used in Testbenches
– Multiple initial blocks start execution in parallel at time 0 and end
independent of other blocks
Examples: initial begin
a = 3’b0;
initial temp_var = 5’b10101; #10 clr = 1’b0;
#21 clr = 1’b1;
end
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 Procedural Blocks . . . .
always:
– Used to describe the functionality of a system
– As the name suggests this block executes always
– It is active as long as simulation is running
– Will synthesize into hardware as defined by statements written
inside the block
– More than one statement requires to be grouped with ‘begin’ &
‘end’
– Can have a sensitivity list which controls when the block will be
executed
– Multiple ‘always’ blocks execute in parallel
– Block becomes active at time 0

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 always block
Example:
module comparator( variables being updated
output reg dgv, dlv, dev, in ‘always’ block need to be
input [4:0] data, value); declared as of type reg

always@(data, value)
begin block will be executed
dgv = (data > value); whenever there is change in
dlv = (data < value); value of ‘data’ or ‘value’
dev = (data == value); - sensitivity list
end
if data is greater than value ‘dgv’ will
endmodule get value 1’b1

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 always - example
module divider #(parameter n = 8)
always block
(output reg [n-1:0] quotient, remainder, without sensitivity
input [n-1:0] dividend, divisor); list. Without timing
control will
act like infinite
always
loop
begin
quotient = #2 dividend / divisor;
#7 remainder = dividend % divisor;
end intra assignment
delay
inter assignment
endmodule delay

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 Sensitivity list
• An always block may or may not have any sensitivity list
• An always block without sensitivity list and no timing control
statements will act like an infinite loop
• The sensitivity list can have the * operator, which means change in
any variable
• If combinational design is being modeled, hardware inferred is not
affected by the sensitivity list
• Example
– always
– always@(a,b,c)
– always@(*)
mean the same
– always@*

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 Timing Control
• Procedural blocks can have timing controls
• These will stop/ delay the simulator from executing the remaining
piece of code until some condition is true
• There are 2 kinds of timing controls
• Delay Based (Postpones the simulation for some time)
• #7 remainder = dividend % divisor;
– Inter assignment delay, will stop the execution of the line for 7 time
units
• quotient = #2 dividend / divisor;
– Intra assignment delay, will evaluate RHS but update LHS after 2
time units
– Equivalent to
» quotient_temp = dividend/divisor;
» #2 quotient = quotient_temp;

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 Timing Control …..
• Event Based (Suspends the simulation for some time)
– always@(data, value)
• will wait for change in value of ‘data’ or ‘value’ to enter the block
• simulator will be in suspended state till data or value changes
• It is as though some signals of the design were being assigned
some priority
– wait(enable)
• will wait for ‘enable’ to have a value
• simulator will be suspend till enable becomes 1

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 Initial & Always Block
Initial Always
– Runs when simulation – Runs when simulation
starts starts
– Terminates when control – Restarts when control
reaches the end reaches the end
– Good for providing – Good for describing
stimulus functionality
– Used in testbenches – Used in designs and is
– Not synthesizable synthesizable
– Will not have sensitivity – May have a sensitivity list
list

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 Procedural assignment statements

• Statements written inside procedural blocks are known as

procedural assignment statements
• They primarily update variables of data type register
• There are two sub-classes known as
– conditional assignment statements
• if-else, case
– loop statements
• for, while, forever, repeat
• Some synthesize while others do not

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 Conditional statement
• This is the behavioural equivalent of the conditional operator
• It can be nested as many times as needed
• Written only inside procedural blocks
• Causes a conditional branch
• When written properly will infer a multiplexer or mux like structure
• Example
module add_sub
Subtractor
(output reg [8:0] result, 0
input [7:0] A, B, input sel); result
always@(A,B,sel) 1
Adder
if(sel) result = A + B;
else result = A – B;
sel
endmodule
Note : If sel is one result will be A+B else if sel is 0, x, z result will be A -B

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 If statement
• A branch of the condition can have more than one statements
grouped with ‘begin’ and ‘end’
• The else condition can be omitted – not at all recommended
• Without proper care will fetch a latch – most prominent cause for
design failure
• No ‘then’ and ‘elsif’ in Verilog
• Example
module 4_1 multiplexer(………….
module latch
…………..
(output reg q, always @(select, a, b, c, d)
input a, gate); begin
out = d;
always@(a,gate) if (select == 2’b00) out = a;
if (select == 2’b01) out = b;
if(gate) q = a; if (select == 2’b10) out = c;
end
endmodule endmodule
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 If example
module latches_two if(lsb)
(output reg y,z, begin
input a,b,sel); acc = acc + multiplicand;
acc = acc >> 1;
always@(*) count = count + 1’b1;
if (sel) y = a; end
else z = b; else
begin
endmodule acc = acc >> 1;
count = count +1’b1;
end
This code will also result in latches

More than one statement in conditional

branch should be grouped with begin and
end

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 If …..
module mux_8_1
(output reg z,
input i0, i1, i2, i3, i4, i5, i6, i7,
input [2:0] s);

always
if (s == 3’d0) z = i0;
else if (s == 3’d1) z = i1;
else if (s == 3’d2) z = i1;
else if (s == 3’d3) z = i1;
else if (s == 3’d4) z = i1;
else if (s == 3’d5) z = i1;
else if (s == 3’d6) z = i1;
else if (s == 3’d7) z =
i1;

endmodule
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 Case Statement
• Multiple branch statement
• Can be equated to multiple if-else statements
• Well constructed case statement will result in multiplexer
• Starts with keyword ‘case’ and ends with ‘endcase’
• There are three variants of the case statement
– case, casez, casex
– example
case(sel) case selector
2’b00 : z = i0;
2’b01 : z = i1;
2’b10 : z = i2;
2’b11 : z = i3;
endcase
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 Case example
• For a n bit case selector there should be 2n branches
• In case 2n branches are not possible, case should have a default
statement
• Case statement can also be nested
• Example
case({a,b,c})
selector is concatenation
3’b000: begin
case(sel)
of 3 single bit variables
1’b0 : ………..
nested case 1’b1 : ………..
endcase
3’b001 : ………………………. 3 bit select line
3’b010 : ………………………. requires 8 branches. When
default : ………………………. 8 operations not available
endcase use default statement

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 Casex, Casez
• Case statement can detect x & z, i.e it makes an exact
match - can equate to string matching
– Example
case(pqr)
3’b0xz: // will work if and only if xyz has the value 3’b0xz
• Casez ignores ‘z’ value in case item
• Casex ignores ‘x’ and ‘z’ value in case item
– Example
casez(pqr)
3’b0xz: // z will be treated as don’t care.
casex(pqr)
3’b0xz: // x as well as z will be treated as don’t care. condition will
// execute if MSB of pqr is zero

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 Casex example
• Uses x, z, and ? as single-bit wildcards in case item and
expression
• Uses first match encountered
– Example

always @ (code)
casex (code) // case expression
2’b0?: control = 8’b00100110; // case item1
2’b10: control = 8’b11000010; // case item 2
2’b11: control = 8’b00111101; // case item 3
endcase

• What is the output for code = 2’b01?

• What is the output for code = 2’b1x?

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 Casez example
• Uses z, and ? as single-bit wildcards in case item and
expression
• Uses first match encountered
– Example

always @ (code)
casez (code)
2’b0?: control = 8’b00100110; // item 1
2’bz1: control = 8’b11000010; // item 2
default: control = 8b’xxxxxxxx; // item 3
endcase

• What is the output for code = 2b’zz?

• What is the output for code = 2b’01?

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 Case revisited
• It can be used only within always/ initial block
• A well constructed case statement should update the same variable
in all the branches
• A well constructed case statement should be both full and parallel
• Full case :
– For n bit select line (case expression) there shall be 2 n branches (case items)
• Parallel Case :
– All the selection options should be unique
– Example
casex(abc)
3’b000 : …………. branch conditions not unique
3’b00x : …………
3’b001 : …………
• Use the “Pragmas” full_case, parallel_case
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 Pragma
module alu #(parameter size = 5)
( output reg [2*size-1:0] result,
input [size-1:0] data_1, data_2,
input [2:0] operation);
Pragmas are
synthesis directives,
always@(operation, data_1, data_2)
which pass some
(* full_case *) case(operation)
information to the
3’b000 : result = data_1 + data_2;
synthesis tools.
3’b001 : result = data_1 – data_2;
Also known as
3’b010 : result = data_1 + 1’b1;
attributes.
3’b011 : result = data_1 – 1’b1;
3’b100 : result = data_1 * data_2;
endcase

endmodule

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 Loops
• Verilog has also loop statements just as in C
• Thee are four loop statements which are used in
procedural blocks
• Repeat, while, forever and for
– Repeat: As the name suggests this is used to repeat a set of
statements for a predefined number of times
– While : Same as in C, used to execute a set of statements when a
given condition is true
– Forever : Again as the name suggests used to forever execute a
set of statements
– For: Same as in C, has a initialization block, condition and
increment/decrement block

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 Repeat
•A repeat loop executes a fixed
number of times, the condition
can be a constant or variable but module count_down();
must have a value integer count;
•If the condition is a variable it is
evaluated only at the entry to the initial
loop and not again during begin
execution count = 128;
repeat(count)
•Example to the right illustrates
count = count + 1’b1;
usage of repeat loop
end
•The loop will execute only 128
times regardless of whether the endmodule
value of count changes once
inside the loop

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 While
•While loop executes when the
condition is true
// Increment count from 0 to 127 ,
•The condition can be any logical // exit at 128
expression
integer count;
•More than one statement can be initial
written in the loop using the begin
begin and end keywords count = 0;
while (count<128)
•Example to the right illustrates count = count +1;
usage of while loop end
•Construct will not synthesize

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 Forever
•The forever loop executes
continuously until the simulation
reg clock;
is exited by some means
•It can be considered to be a
initial
while loop in which condition
never becomes false begin
•The forever loop must be used clock = 1’b1;
with a timing control to limit its forever #5 clock = ~ clock;
execution failing which the loop end
would be executed continuously
at the expense of other statements initial #2000 $finish;
•Typically used in testbenches to
generate clock waveform
•Will not synthesize

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 For loop
•The for loop syntax is same as
that in C module for_example
•It has three parts, (output reg [7:0] XOR,
– The first part – initialization – input [7:0] A,B);
which is executed once before
the loop is entered reg [3:0] j;
– The second part – test – when
true causes the loop to re- always@(A,B)
iterate for(j = 0; j <= 4’d7; j = j + 1)
– The third part – variable XOR[count] = A[j] ^ B [j];
update – which is executed at
the end of each iteration endmodule

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 For loop
• The only loop that is synthesizable
• Can be made to work like forever loop
– for(j = 1; j> 0; j = j+ 1) // condition never fails –will not synthesize
• Can be made to work like repeat loop
– for(j=0; j < 10; j = j + 1) // repeat 10 times – will synthesize
• Can be made to work like while loop with appropriate test
condition
• For loop synthesizes if only the number of times the for loop will
iterate can be determined from the test condition before the code
can be synthesized
• Executes in zero time, hence needs to be thoughtfully used in
designs

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 Summary
• Verilog behavioural modeling has been discussed
• Various data types and their association with ports has
been understood
• Procedural blocks have been analyzed
• Procedural assignment statements and their operation has
been studied
• Timing control operators have been discussed
• Conditional assignment statements and hardware inference
has been thoroughly discussed
• Delegate has been made aware about Pragmas / synthesis
directives
• Looping assignment statements has been studied
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