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Eec 455-LPVD-M1-V3

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Girish Shankar Mishra
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14 views22 pages

Eec 455-LPVD-M1-V3

Uploaded by

Girish Shankar Mishra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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GITAM

(Deemed to be University)
Bengaluru Campus
School of Technology

EEC 455 LOW POWER VLSI


DESIGN
Presented By
Girish Shankar Mishra
Assistant Professor
Department of EECE
Module-1
Introduction

• Contents
 Need for low power design
 Leakage and its contribution to IC power
 Trends in leakage power
 Physics of power dissipation in CMOS devices
 Power dissipation in CMOS
 Low power VLSI design limits
Increasing Challenges of Power
 Increasing device densities
 Increasing clock frequencies
 Lowering supply voltage
 Lowering transistor threshold voltage

High power consumptionhigher temperatureheat sinks, ceramic packaging


(expensive)

Power Management

 Manage power in all modes of operation


 Dynamic power during device operation, Static power during standby
 Maintain device performance while minimizing power consumption
 Performance available when required
 Power minimized while providing required performance
Types of Power
Consumption
Dynamic power

 During the switching of transistors


 Depends on the clock frequency and switching activity
 Consists of switching power and internal power.

Static Power

 Transistor leakage current that flows whenever power is


applied to the device
 Independent of the clock frequency or switching
activity.
Dynamic
Power

one transistor
is ON at a
time

Instantaneous 0 to 1 on the output


rise time charges the
capacitive load of
the PMOS

1 to 0 on the output
discharges the
capacitive load
through the
NMOS
Dynamic Power Contd....
Vdd

Pavg=Cload.Vdd2.Fclk
A
PMOS
average power is
Vout independent of
B Cdrain+
NMOS CloadCinterconnect transistor size and
+
Cinput
characteristics

Cload depends on:

• Output node capacitance of the logic gate: due to the drain


diffusion region.
• Total interconnects capacitance: has higher effect as technology
node shrinks.
• Input node capacitance of the driven gate: due to the gate oxide
capacitance.
Internal power
 Power consumed by the cell when an input changes, but output does not
change

 Internal node voltage swing can be only Vi which can be smaller than the
full voltage swing of Vdd leading to the partial voltage swing.

How to reduce dynamic power? Vdd

A
PMOS
Vout
Pavg α Cload.Vdd2.Fclk Cload
B Cdrain+
NMOS
Cinterconnect
+
Reduce Vdd Cinput

Reduce Cload
Reduce Fclk
Short Circuit
Power
Finite rise and fall time
VTn < Vin < Vdd - |VTp|

Both PMOS and NMOS are


Intermediate
conducting for a short duration of voltage
time

short between supply power and


ground

Lower threshold voltages and


slower transitions result in more
internal power consumption.
Short Circuit Power-
Analysis More rise/fall timemore short circuit
Lower threshold voltagemore short
Condition PMOS NMOS circuit
Vdd- |Vthp|
Vin <
ON (sat) OFF (cutoff) 2.5V
Vth PMOS
curve
Linear Linear
Vin =
(towards (towards
Vth Vout Vthn<Vin<Vdd-|Vthp|
cutoff) sat)
NMOS
Vin >
OFF (cutoff) ON (sat) curve
Vth
0V Vthn
Vin 2.5V

Pavg(short circuit) = 1/12.k.τ.Fclk.(Vdd-2Vt)3

To get equal rise/fall  balance transistor sizing


If Vdd<Vthn+|Vthp| can we eliminate short circuit Q
current?????
Leakage Power

Diode reverse bias current or


Reverse-biased, drain- and source-
substrate junction band-to-band-
tunneling (BTBT) –I1

 Sub threshold current – I2

 Gate induced drain leakage – I3

 Gate oxide tunneling – I4


Leakage Power
Contd....
-does not depend on input transition, load capacitance
-remains constant
Reverse Biased Diode Current (Junction
Leakage)-I1
Parasitic diodes formed between the
diffusion region of the transistor
and substrate

Ireverse=A.Js.(e(q.Vbias/kT)-1)
where,
Vbias --> reverse bias voltage across the junction
Js --> reverse saturartion current density
A --> junction area

How to reduce?
Decrease in junction area  depends material
Reverse Biased Diode Current
(Junction Leakage)-I1 Contd…
Subthreshold

Gate leakage
leakage

ON OFF p-n junction


Subthreshold leakage

leakage
from n-well 0
0 1
1

OFF p-n junction ON


Gate leakage to
substrate
leakage
Sub threshold Current – I2 (Isub)
Always flows from source to
ON
drain Subthreshold
leakage
Vgs <~ Vth carrier diffusion 0 1

causes sub threshold leakage OFF p-n junction


Gate leakage to
leakage substrate
 Vgs<=0 accumulation mode
 0<Vgs<<Vthdepletion mode
 Vgs~Vth weak inversion Subthreshold
Gate
leakage
 Vgs>VthInversion leakage
OFF p-n junction
leakage
from n-well
1 0

ON
How to reduce sub threshold
leakage?

Isub exponentially scales with Vth vary Vth

 Higher Vth results in lower leakage, longer delay


 Optimize the design with the balance application of low
Vth (LVT) and high Vth devices (HVT).
 Older technologies - more threshold variation
 Newer technologies produce around 30 mV threshold
variation

Does this equation valid below 90nm???? Q


Gate Induced Drain Leakage
(GIDL) - I3
Caused by high field effect in the drain
junction of MOS transistors

When Vgs <= 0V; Vd = Vdd


avalanche multiplication and band-to-band
tunneling
Minority carriers underneath the gate are
swept to the substrate

GIDL increases with:


 Higher supply voltage
 thinner oxide
 increase in Vdb and Vdg.
Band to Band Tunneling
Gate Oxide Tunnelling - I4
 Due to high electric field across a thin gate oxide

Fowler-Nordheim tunneling: conduction band


of the oxide layer

Direct tunneling through the silicon oxide layer if it is less than 3–


4 nm thick
How to reduce gate leakage?

Improve fab chemistry

Reached fundamental limit of gate oxide thickness???? Q


Gate Leakage Current

How to reduce?
Components of Leakage power
Leakage Power Trends
leakage current increases
Scaling: Boon or Curse??? exponentially.
Should be done for Voltage and Threshold Leakage power is catching
voltage to gain the performance up with Dynamic Power.

 At 90 nm and below, leakage power management is essential.


 Thinner gate oxides have led to an increase in gate leakage current.
Thank you

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