module HA_behave (input a,

HALF ADDER & TEST BENCH input b,

output sum,
module HA_dataflow (
module HA_tb(); output carry);
input a,
input b, reg a, b;
wire sum, carry; reg sum, carry;
output sum,
always @ (a or b)
output carry);
HA_dataflow U1(a,b,sum,carry) begin
assign sum = a ^ b ;
sum = a ^ b ;
assign carry = a & b;
initial carry = a & b;
endmodule
begin end
#0 a=0;b=0;
#10 a=0;b=1; endmodule
#10 a=1;b=0;
#10 a=1;b=1;
module HA_gate(a, b, sum,
end
carry);
initial
input a, b;
$monitor($time,”a=%b,b=%b,sum=%b,carry=%b”,a,b,sum,carry);
output sum, carry;
initial
xor (sum, a, b);
#50 $finish;
and (carry, a, b);
endmodule
endmodule
FULL ADDER & TEST BENCH module FA_behave(a, b, cin, sum, carry);
input a, b, cin;
module FA_Data(a, b, cin, sum, module FA_tb(); output sum, carry;
carry); reg a,b,cin; wire sum, carry;
input a, b, cin; wire sum,carry; always @ (aor b or cin)
output sum, carry; begin
assign sum = a^b^cin; FA_behave U1(a,b,cin,sum,caary); sum = a^b^cin;
assign carry = (a&b)|(b&cin)|(a&cin); carry = (a&b)|(b&cin)|(a&cin);
endmodule initial end
begin endmodule
#0 a=0;b=0;cin=0;
#10 a=0;b=0,cin=1; module FA_gate(a, b, cin, sum, carry);
#10 a=0;b=1,cin=0; input a,b,cin;
#10 a=0;b=1,cin=1; output sum, carry;
#10 a=1;b=0;cin=0; wire s,t,u;
#10 a=1;b=0,cin=1; xor (s, a, b);
#10 a=1;b=1,cin=0; and (t,a,b);
#10 a=1;b=1,cin=1; xor (sum, s, cin);
#10 $stop; and (u,s,cin);
end or (carry,u,t);
endmodule endmodule
 //////////////////////////////
RIPPLE CARRY ADDER //1bit Full Adder
//////////////////////////////////// /////////////////////////////
//4-bit Ripple Carry Adder
//////////////////////////////////// module full_adder(a,b,cin,sum, cout);
input a,b,cin;
module ripple_carry_4_bit(a, b, cin, sum, cout); output sum, cout;
input [3:0] a,b; wire x,y,z;
input cin; half_adder h1(.a(a), .b(b), .sum(x), .cout(y));
wire c1,c2,c3; half_adder h2(.a(x), .b(cin), .sum(sum), .cout(z));
output [3:0] sum; or or_1(cout,z,y);
output cout; endmodule

full_adder fa0(.a(a[0]), .b(b[0]),.cin(cin), .sum(sum[0]),.cout(c1)); ///////////////////////////

full_adder fa1(.a(a[1]), .b(b[1]), .cin(c1), .sum(sum[1]),.cout(c2)); // 1 bit Half Adder
full_adder fa2(.a(a[2]), .b(b[2]), .cin(c2), .sum(sum[2]),.cout(c3)); //////////////////////////
full_adder fa3(.a(a[3]), .b(b[3]), .cin(c3), .sum(sum[3]),.cout(cout));
endmodule module half_adder( a,b, sum, cout );
input a,b;
output sum, cout;
xor xor_1 (sum,a,b);
and and_1 (cout,a,b);
endmodule
RIPPLE CARRY ADDER TESTBENCH

module ripple_carry_4_bit_tb();
reg [3:0]a,b;
reg cin;
wire [3:0]sum;
wire carry;

ripple_carry_4_bit U1(a,b,cin,sum,carry);

initial
begin

#0 a=4’b1010;b=4’b0011;cin=0;
#10 a=4’b1100; b=4’b0101; cin=1’b1;
end
initial
$monitor(“time=“,$time, “a=%b,b=%b,cin=%b,sum=%b,carry=%b”,a,b,cin,sum,carry);
initial
#30 $finish;
endmodule
2 BIT COMPARATOR AND TESTBENCH
module 2_Mag_Comp(input [1:0]a, b, output equal, module comparator_tb();
greater, lower ); reg [1:0]a,b;
reg greater, equal, lower; wire equal,greater,lower;
initial greater = 0, equal = 0, lower = 0;
always @ (a or b) Mag_Comp U1(a,b,equal,greater,lower);
begin initial
if (a < b) begin
begin #0 a=2’b01;b=2’b10;
greater = 0; equal = 0; lower = 1; #10 a=2’b11;b=2’b11;
end #10 a=2’b11; b=2’b01;
else if (a == b) end
begin initial
greater = 0; equal = 1; lower = 0; $monitor($time,”a=%b,b=%b,equal=%b,greater=%b,lower=
end %b”,a,b,equal,greater,lower);
else Initial
begin #50 $finish;
greater = 1; equal = 0; lower = 0; endmodule
end
end
endmodule
4:1 MULTIPLEXER & TEST BENCH
module mux4to1_tb( );
module mux4to1(i, s, y); reg [3:0] i;
input [3:0] i; reg [1:0] s;
input [1:0] s; wire y;
output reg y; mux4to1 g1(i, s, y);
always @ (*) initial
if (s==0) begin
y=i[0]; #0 s=2'b00; i=4'b0001;
else if (s==1) #10 s=2'b01; i=4'b0001;
y=i[1]; #10 s=2'b10; i=4'b0101;
else if (s==2) #10 s=2'b11; i=4'b1001;
y=i[2]; end
else initial
y=i[3]; $monitor ($time, "i = %b, s=%b, y=%b", i, s, y);
endmodule
initial
#100 $finish;
endmodule
8:1 MULTIPLEXER & TEST BENCH
module mux8to1_tb( );
module mux8to1(i, s, y); reg [7:0] i;
input [7:0] i; reg [2:0] s;
input [2:0] s; wire y;
output reg y; mux8to1 g1(i, s, y);
always @ (*) initial
begin begin
case (s) #0 s=3'b000; i=8'b10101010;
3'b000: y=i[0]; #10 s=3'b001; i=8'b10101010;
3'b001: y=i[1]; #10 s=3'b010; i=8'b10101010;
3'b010: y=i[2]; #10 s=3'b011; i=8'b10101010;
3'b011: y=i[3]; #10 s=3'b100; i=8'b10101010;
3'b100: y=i[4]; #10 s=3'b101; i=8'b10101010;
3'b101: y=i[5]; #10 s=3'b110; i=8'b10101010;
3'b110: y=i[6]; #10 s=3'b111; i=8'b10101010;
3'b111: y=i[7]; end
default: y=8'b00000000; initial
endcase $monitor ($time, "i = %b, s=%b, y=%b", i, s, y);
end
endmodule initial
#100 $finish;
endmodule