Digital Logic Design I

Simplification of Boolean
Functions

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 3-1 Introduction
 Gate-level minimization refers to the design task of
finding an optimal gate-level implementation of Boolean
functions describing a digital circuit.

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 3-2 The Map Method
 The complexity of the digital logic gates
 The complexity of the algebraic expression
 Logic minimization
 Algebraic approaches: lack specific rules
 The Karnaugh map k-map
 A simple straight forward procedure
 A pictorial form of a truth table
 Applicable if the # of variables < 7
 A diagram made up of squares
 Each square represents one minterm

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Review of Boolean Function
 Boolean function
 Sum of minterms
 Sum of products (or product of sum) in the simplest form
 A minimum number of terms
 A minimum number of literals
 The simplified expression may not be unique

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Two-Variable Map
 A two-variable map
 Four minterms
 x' = row 0; x = row 1
 y' = column 0; y =
column 1
 A truth table in square
diagram
 Fig. 3.2(a): xy = m3 Figure 3.1 Two-variable Map
 Fig. 3.2(b): x+y =
x'y+xy' +xy =
m1+m2+m3

Figure 3.2 Representation of functions in the map

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A Three-variable Map
 A three-variable map
 Eight minterms
 The Gray code sequence
 Any two adjacent squares in the map differ by only on variable
 Primed in one square and unprimed in the other
 e.g., m5 and m7 can be simplified
 m5+ m7 = xy'z + xyz = xz (y'+y) = xz

Figure 3.3 Three-variable Map

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A Three-variable Map
 m0 and m2 (m4 and m6) are adjacent
 m0+ m2 = x'y'z' + x'yz' = x'z' (y'+y) = x'z'
 m4+ m6 = xy'z' + xyz' = xz' (y'+y) = xz’
 m0+m1+m3+m2= xy’z’+x’y’z+x’yz+x’yz’=x’
 m4+m5+m7+m6=xy’z’+xy’z+xyz+xyz’=x

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 A Three-variable Map
 m0+m4= x’y’z’+xy’z’ = y’z’
 m1+m5=x’y’z+xy’z=y’z
 m3+m7= x’yz+xyz =yz
 m2+m6= x’yz’+xyz’ =yz’

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 A Three-variable Map
 m0+m4= x’y’z’+xy’z’ = y’z’
 m1+m5=x’y’z+xy’z=y’z
 m3+m7= x’yz+xyz =yz
 m2+m6= x’yz’+xyz’ =yz’


xyz 00 01 11 10

0 m0 m1 m3 m2
(x’y’z’) (x’y’z) (x’yz) (x’yz’)
1 m4 m5 m7 m6
(xy’z’) (xy’z) (xyz) (xyz’)

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 Example 3.1
 Example 3.1: simplify the Boolean function F(x, y, z) =
S(2, 3, 4, 5)
 F(x, y, z) = S(2, 3, 4, 5) = x'y + xy'

Figure 3.4 Map for Example 3.1, F(x, y, z) = Σ(2, 3, 4, 5) = x'y + xy'

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 Example 3.2
 Example 3.2: simplify F(x, y, z) = S(3, 4, 6, 7)
 F(x, y, z) = S(3, 4, 6, 7) = yz+ xz’
 YZ+XZ’+XY

Figure 3.5 Map for Example 3-2; F(x, y, z) = Σ(3, 4, 6, 7) = yz + xz'

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Four adjacent Squares
 Consider four adjacent squares
 2, 4, and 8 squares
 m0+m2+m4+m6 = x'y'z'+x'yz'+xy'z'+xyz' = x'z'(y'+y) +xz'(y'+y) =
x'z' + xz‘ = z'
 m1+m3+m5+m7 = x'y'z+x'yz+xy'z+xyz =x'z(y'+y) + xz(y'+y) =x'z
+ xz = z

Figure 3.3 Three-variable Map

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 Example 3.3
 Example 3.3: simplify F(x, y, z) = S(0, 2, 4, 5, 6)
 F(x, y, z) = S(0, 2, 4, 5, 6) = z'+ xy'

Figure 3.6 Map for Example 3-3, F(x, y, z) = Σ(0, 2, 4, 5, 6) = z' +xy'
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Example 3.4
 Example 3.4: let F = A'C + A'B + AB'C + BC
a) Express it in sum of minterms.
b) Find the minimal sum of products expression.
Ans:
F(A, B, C) = S(1, 2, 3, 5, 7) = C + A'B

Figure 3.7 Map for Example 3.4, A'C + A'B + AB'C + BC = C + A'B
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January 4, 2025 15
 Example 3.4
Obtain simplified expressions in sum of products
 F = XY+X’Y’Z’+X’YZ’
 F=A’B+BC’+B’C’ =C’+A’B
 F=D(A’+B)+B’(C+AD) = D+B’C
 F(A,B,C,D)=Σ(2,3,12,13,14,15)==AB+A’B’C
 F=A’B’C’D’+AC’D’+B’CD’+A’BCD+BC’D
==B’D’+A’BD+ABC’
 F=BDE+B’C’D+CDE+A’B’CE+A’B’C+B’C’D’E’
= DE+A’B’C+B’C’E’

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3.3 Four-Variable Map
 The map
 16 minterms
 Combinations of 2, 4, 8, and 16 adjacent squares

January 4, 2025 Figure 3.8 Four-variable Map

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3.3 Four-Variable Map
 for map minimization
 One square represents one minterm, giving a term of
four literals.
 Two squares represent a term of three literals.
 Four squares represent a term of two literals.
 Eight squares represent a term of one literal.
 Sixteen squares represent the function equal to 1.

January 4, 2025 Figure 3.8 Four-variable Map

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 Example 3.5
 Example 3.5: simplify F(w, x, y, z) = S(0, 1, 2, 4, 5, 6, 8,
9, 12, 13, 14) =Y’+W’Z’+XZ’

F = y'+w'z'+xz'

Figure 3.9 Map for Example 3-5; F(w, x, y, z) = Σ(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) = y' + w' z' +xz'
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Example 3.6
 Example 3-6: simplify F = ABC + BCD + ABCD +
ABC

=A’B’C’(D+D’)+(A+A’)B’CD’+A’B’C’D’+AB’C’(D+D’)
=A’B’C’D+A’B’C’D’+AB’CD’+A’B’CD’+A’BCD’+AB’C’D+AB’
C’D’
=0001+0000+1010+0010+0110+1001+1000
 =(0,1,2,6,8,9,10)

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 Example 3.6
 Example 3-6: simplify F = ABC + BCD + ABCD +
ABC
 B’C’+B’D’+A’CD’

Figure 3.9 Map for Example 3-6; ABC + BCD +

ABCD + ABC= BD + BC +ACD

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Prime Implicants
 Prime Implicants
 All the minterms are covered.
 Minimize the number of terms.
 A prime implicant: a product term obtained by combining the
maximum possible number of adjacent squares (combining all
possible maximum numbers of squares).
 Essential P.I.: a minterm is covered by only one prime
implicant.
 The essential P.I. must be included.

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 Prime Implicants
 Consider F(A, B, C, D) = Σ(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)
 The simplified expression may not be unique
 F = BD+B'D'+CD+AD = BD+B'D'+CD+AB'
= BD+B'D'+B'C+AD = BD+B'D'+B'C+AB'

January 4, 2025Figure 3.11 Simplification Using Prime Implicants 23

3.4 Five-Variable Map
 Map for more than four variables becomes complicated
 Five-variable map: two four-variable map (one on the top of the
other).

January 4, 2025 Figure 3.12 Five-variable Map

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 Table 3.1 shows the relationship between the number of
adjacent squares and the number of literals in the term.

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 Example 3.7
 Example 3.7: simplify F = S(0, 2, 4, 6, 9, 13, 21, 23, 25,
29, 31)

F = A'B'E'+BD'E+ACE
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 3-5 Product of Sums Simplification
 Approach #1
 Simplified F' in the form of sum of products
 Apply DeMorgan's theorem F = (F')'
 F': sum of products → F: product of sums
 The 1’s marked in the map represent all the minterms of
the function F.
 The 0’s marked in the map represent all the minterms not
included in F means complement of function F that is F’.
 Combined all 1’s mark squares gives simplified F(SOP).
 Combined all 0’s mark squares gives simplified F’(SOP).
 Apply DeMorgan’s on F’ gives simplified F(POS).

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 Example 3.8
 Example 3.8: simplify F = S(0, 1, 2, 5, 8, 9, 10) into (a)
sum-of-products form, and (b) product-of-sums form:

a) F(A, B, C, D)= S(0, 1, 2, 5,

8, 9, 10) =
B'D'+B'C'+A'C'D
b) F' = AB+CD+BD'
» Apply DeMorgan's theorem;
F=(A'+B')(C'+D')(B'+D)
» Or think in terms of maxterms

Figure 3.14 Map for Example 3.8, F(A, B, C, D)= S(0,

1, 2, 5, 8, 9, 10) = B'D'+B'C'+A'C'D
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 Example 3.8 (cont.)
 Gate implementation of the SOP AND POS.
 Implementation of standard form is said to be a two-
level implementation.

Sum-of products Product-of sums

form form

Figure 3.15 Gate Implementation of the Function of Example 3.8

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 Sum-of-Minterm Procedure
 Consider the function defined in Table 3.2.
 In sum-of-minterm:

F ( x, y , z )  (1,3, 4,6)
 In sum-of-maxterm:
(complement of F)

F ( x, y , z ) (0, 2,5,7)

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 Sum-of-Minterm Procedure
 Consider the function defined in Table 3.2.
 Combine the 1’s:

F ( x, y , z )  xz  xz 
 Combine the 0’s :

F'( x, y , z )  xz  xz 
 Taking the Demorgan’s of F’
POS: F=(X’+Z’)(X+Z)

Figure 3.16 Map for the function of Table 3.2

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 If function expressed in POS ask to present in map,
Take the complement of the function and from it find the
squares to be marked by 0’s.
F=(A’+B’+C)(B+D)
F’=ABC’+B’D’
And then marking 0’s in the squares representing the
minterms of F’. The remaining squares are marked with
1’s. '

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 EXAMPLES
 Obtain the simplified expressions in POS,sop:
F(x,y,z)= p(0,1,4,5) =Y

X yz 00 01 11 10

0 0 0 1 1
1 0 0 1 1
F’=y’
(F’)’=Y (pos)
F=Y (SOP)

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EXAMPLES
 Obtain the simplified expressions in POS:
F(A,B,C,D)=P(0,1,2,3,4,10,11)= (B+C’)(A+B)(A+C+D)
Combine 0’s complement of sop
F’= A’B’+A’C’D’+B’C
(F’)’ = (A’B’+A’C’D’+B’C)’
POS=(A+B)(A+C+D)(B+C’)--pos
'
Combine 1’s SOP
F= BC+BD+AC’

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EXAMPLES
 Obtain the simplified SOP and POS And implement
using AND and OR gates.

F=(A+B’+D)(A’+B+D)(C+D)(C’+D’)
Find DeMorgan’s of F is
F’=A’BD’+AB’D’+C’D’+CD

Combine 1’s F(sop)= C’D+ABCD’+A’B’CD’

Combine 0’s F’= C’D’+CD+AB’D’+A’BD’

Take DeMorgan’s of F’= (F’)’(pos)= (C+D)(C’+D’)(A’+B+D)

(A+B’+D)

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 3-6 Don't-Care Conditions
 The value of a function is not specified for certain
combinations of variables
 BCD; 1010-1111: don't care
 The don't-care conditions can be utilized in logic
minimization
 Can be implemented as 0 or 1
 Example 3.9: simplify F(w, x, y, z) = S(1, 3, 7, 11, 15)
which has the don't-care conditions d(w, x, y, z) = S(0,
2, 5).

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Example 3.9 (cont.)
 F = yz + w'x'; F = yz + w'z
 F = S(0, 1, 2, 3, 7, 11, 15) ; F = S(1, 3, 5, 7, 11, 15)
 Either expression is acceptable
 Combine 1’s

Figure 3.17 Example with don't-care Conditions

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Example 3.9 (cont.)
 F = yz + w'x'; F = yz + w'z
 F = S(0, 1, 2, 3, 7, 11, 15) ; F = S(1, 3, 5, 7, 11, 15)
 Combine 0’s

F’=Z’ + WY’
(F’)’= Z(W’+Y) --POS

Figure 3.17 Example with don't-care Conditions

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Example
 F=W’(X’Y+X’Y’+XYZ)+X’Z’(Y+W)
 d=W’X(Y’Z+YZ’)+WYZ = W’XY’Z+W’XYZ’+WYZ
 F=W’X’Y+W’X’Y’+W’XYZ+X’YZ’+WX’Z’

Simplify sop and pos

Combine 1’s
F= x’z’+w’z --sop
Combine 0’s
F’= xz’+wz

Take De-Morgan’s
(F’)’ =F= (x’+z)(w’+z’)---pos

Figure 3.17 Example with don't-care Conditions

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Example
 F=ACE+A’CD’E’+A’C’DE d=DE’+A’D’E+AD’E’
 F= AC+CD’+A’C’D ---SOP ---Combine 1’s
 F’= AC’+A’CD+C’D’--sop’ --- combine 0’s
 (F’)’=F= (A’+C)(C+D)(A+C’+D’)--POS

Figure 3.17 Example with don't-care Conditions

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Example
 F=(A+D) (A’+B)(A’+C’)
 F’=A’D’+AB’+AC
 Combine all 1’s

F= ABC’+A’D ---sop

Using NAND gate not more than

Three gates.

Figure 3.17 Example with don't-care Conditions

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3-7 NAND and NOR Implementation
 NAND gate is a universal gate
 Can implement any digital system

Figure 3.18 Logic Operations with NAND Gates

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NAND Gate
 Two graphic symbols for a NAND gate

Figure 3.19 Two Graphic Symbols for NAND Gate

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NAND Implementation
 For NAND Gates implementation: SOP
F= AB+CD+E

Figure
January 4, 2025 3.20 Three ways to implement F = AB + CD
44
 NAND Implementation
 Two-level logic
 NAND-NAND = sum of products
 Example: F = AB+CD
 By using DeMorgan’s theorem
 F = ((AB)' (CD)' )' =AB+CD

Figure
January 4, 2025 3.20 Three ways to implement F = AB + CD
45
 Example 3.10
 Example 3-10: implement F(x, y, z) = Σ(0,6)
Uisng k-map Yz 00 01 11 10
x
0 1 0 0 0
F=x’y’z’+xyz’ sop
1 0 0 0 1
F’= z+ xy’+x’y sop’
((x’y)’(xy’)’z’)’= (x’y)+ (xy’)+z

January 4, 2025 Figure 3.21 Solution to Example 3-10

46
Procedure with Two Levels NAND
 The procedure
 Simplified in the form of sum of products;
 A NAND gate for each product term; the inputs to each NAND
gate are the literals of the term (the first level);
 A single NAND gate for the second sum term (the second
level);
 A term with a single literal requires an inverter in the first level.

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Multilevel NAND Circuits
 Boolean function implementation
 AND-OR logic → NAND-NAND logic
 AND → AND + inverter
 OR: inverter + OR = NAND
 For every bubble that is not compensated by another small circle
along the same line, insert an inverter.

January 4, 2025 Figure 3.22 Implementing F = A(CD + B) + BC 48

NAND Implementation

January 4, 2025 Figure 3.23 Implementing F = (AB +AB)(C+ D)

49
NOR Implementation
 NOR function is the dual of NAND function.
 The NOR gate is also universal.

January 4, 2025
Figure 3.24 Logic Operation with NOR Gates
50
 Two Graphic Symbols for a NOR Gate

Figure 3.25 Two Graphic Symbols for NOR Gate

Example: F = (A + B)(C + D)E

January 4, 2025 Figure 3.26 Implementing F = (A + B)(C + D)E

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NOR Gate

52
 Example

Example: F = (AB +AB)(C + D)

Figure 3.27 Implementing F = (AB +AB)(C + D) with NOR gates

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 Example 3.10
 Example 3-10: implement F(x, y, z) = Σ(0,6)
Uisng k-map Yz 00 01 11 10
x
COMBINE 0’S
0 1 0 0 0
F’= z+ xy’+x’y – sop’
1 0 0 0 1
(F’)’=Z’(X’+Y)(X+Y’)

January 4, 2025 Figure 3.21 Solution to Example 3-10 54

 Example 3.10
 Example 3-10: implement F(x, y, z) = Σ(0,6)
Uisng k-map Yz 00 01 11 10
x
Combine 1’s
0 1 0 0 0
F=x’y’z’+xyz’--sop
1 0 0 0 1
(F)’=(x+y+z)(x’+y’+z)

January 4, 2025 Figure 3.21 Solution to Example 3-10 55

 summary
For NAND gate:
F= sum of products ( combine 1’s in map) 2 level ckt.
F’= sum of products (combine 0’s in map) 3 level ckt.

For NOR gate:

F= product of sums (combine 0’s and take demorgan’s)
( complement of F’(sop)) 2 level ckt.
F’= product of sums(combine 1’s and take demorgan’s)
(complement of F(sop)) 3 level ckt.

January 4, 2025 Figure 3.21 Solution to Example 3-10 56

Simplify the following functions and implement them with
NAND and NOR gates.
F=(B’+D’)(A’+C’+D)(A+B’+C’+D)(A’+B+C’+D’)
F’= BD + ACD’+A’BCD’+AB’CD
Combine 1’s
F= A’B’+C’D’+B’C’ (SOP)
Combine 0’s
F’=BD+BC+AC (sop)’

Take De-Morgans
(F’)’=(BD+BC+AC)’ (P0S)
=(B’+D’)(B’+C’)(A’+C’)

January 4, 2025 Figure 3.21 Solution to Example 3-10 57

Combine 1’s implement using NAND
F= A’B’+C’D’+B’C’ (SOP) gate for F and F’ both.
Combine 0’s
F’=BD+BC+AC (sop)’

Take De-Morgans
(F’)’=F=(BD+BC+AC)’ (P0S) implement using NOR
=(B’+D’)(B’+C’)(A’+C’) gate for F and F’ both.
Take De-Morgans of F
F’= (A+B)(C+D)(B+C) (POS)

January 4, 2025 Figure 3.21 Solution to Example 3-10 58

Implement using NAND gate. Both the normal and
complement inputs are available.
F=BD+BCD+AB’C’D’+A’B’CD’ with no more than six
gates, each having three inputs.
Combine 1’s
F= BD+AB’C’D’+A’B’CD’
=BD+D’(AB’C’+A’B’C)
Combine 0’s
F’= B’D+BD’+AB’C+A’C’D’

January 4, 2025 Figure 3.21 Solution to Example 3-10 59

Implement using NOR gates.
F=AB’+C’D’+A’CD’+ABC’D+A’B’C’D+ABC’D+A’BCD
Combine 0’s
F’= ABC+A’BC’D+A’B’CD (sop)’
Take demorgan’s
(F’)’=F=(A’+B’+C’)(A+B’+C+D’)
(A+B+C’+D’)
Combine 1’s
F=

January 4, 2025 Figure 3.21 Solution to Example 3-10 60

 3-8 Other Two-level Implementations (
 Wired logic
 A wire connection between the outputs of two gates
 Open-collector TTL NAND gates: wired-AND logic
 The NOR output of ECL gates: wired-OR logic = A’B’+C’D’

F ( AB )(CD ) ( AB  CD ) ( A  B)(C   D) AND-OR-INVERT function

F ( A  B )  (C  D ) [( A  B )(C  D )] OR-AND-INVERT function

Figure 3.28 Wired Logic

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Non-degenerate Forms
 16 possible combinations of two-level forms
 Eight of them: degenerate forms = a single operation
 AND-AND, AND-NAND, OR-OR, OR-NOR, NAND-OR, NAND-
NOR, NOR-AND, NOR-NAND.
 The eight non-degenerate forms
 AND-OR, OR-AND, NAND-NAND, NOR-NOR, NOR-OR, NAND-
AND, OR-NAND, AND-NOR.
 AND-OR and NAND-NAND = sum of products.
 OR-AND and NOR-NOR = product of sums.
 NOR-OR, NAND-AND==AOI,
 OR-NAND, AND-NOR =OAI

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AND-OR-Invert Implementation
 AND-OR-INVERT (AOI) Implementation
 NAND-AND = AND-NOR = AOI
 F = (AB+CD+E)’ ((AB)’.(CD)’E’)= (AB+CD+E)’
 F' = AB+CD+E (sum of products)
 SOP– AND-OR /NAND-NAND

Figure 3.29 AND-OR-INVERT circuits, F = (AB +CD +E)

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OR-AND-Invert Implementation
 OR-AND-INVERT (OAI) Implementation
 OR-NAND = NOR-OR = OAI
 F = ((A+B)(C+D)E)’ (A+B)’+(C+D)’+E’ = ((A+B).(C+D).E)’
 F' = (A+B)(C+D)E (product of sums)
 POS--- OR-AND / NOR-NOR

Figure 3.30 OR-AND-INVERT circuits, F = ((A+B)(C+D)E)'

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 Tabular Summary and Examples
 Example 3-11: F = x'y'z'+xyz'
 F' = x'y+xy'+z (F': sum of products)
 F = (x'y+xy'+z)' (F: AOI implementation)
 F = x'y'z' + xyz' (F: sum of products)
 F' = (x+y+z)(x'+y'+z) (F': product of sums)
 F = ((x+y+z)(x'+y'+z))' (F: OAI)

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Tabular Summary and Examples

January 4, 2025 66
January 4, 2025 Figure 3.31 Other Two-level Implementations 67
 The Tabulation Method
 To overcome a difficulty of function simplification of six
or more variables.
 It give guaranteed to produce a simplified standard-
form expression for a function.
 It can applied to problems with many variables.
 It has the advantage of being suitable for machine
computation.
 It is also known as the Quine-McCluskey method.
 Two parts: the first is to find by an exclusive search all
the terms that are candidates for inclusion in the
simplified function. These terms are prime-implicants.
 Choose among the prime-implicants those give an
expression with the least number of literals.
January 4, 2025 68
Determine the prime- implicants

 List of all the minterms that specify the expression.

 Find the prime-implicants by using a matching process.
 In this process, each minterm compare with other
minterm.
 If two minterms differ in only one variable,that variable
removed and a term with one less literal is found.
 Repeat above process until the search is completed.
 More cycles are continued until a single pass through a
cycle yields no further elimination of literals.
 The remaining terms that did not match during the
process comprise the prime-implicants.

January 4, 2025 69
 Example: simplify the Boolean function by using the tabular
method: F= S(0,1,2,8,10,11,14,15)
 Step 1: group binary representation of the minterms
according to the number
W of
X 1’s
Y contained.
Z
0 0 0 0 0 √
col a.
1 0 0 0 1 √

2 0 0 1 0 √

8 1 0 0 0 √

10 1 0 1 0 √

11 1 0 1 1 √

14 1 1 1 0 √

15 1 1 1 1 √

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 W X
Example: simplify Y Boolean
the Z function by using the tabular
0, 1 F=0 S(0,1,2,8,10,11,14,15)
method: 0 0 _
0, 2 0 0 _ 0 √
 Step 2: any two minterms which are differ from each
other
0, 8by only
_ 0one0 variable
0 √can be combined, and
unmatched variable removed.
2, 10 _ 0 1 0 √

8, 10 1 0 _ 0 √

10, 11 1 0 1 _ √
col b.
10, 14 1 _ 1 0 √

11, 15 1 _ 1 1 √

14, 15 1 1 1 _ √

January 4, 2025 71
Example: simplify the Boolean function by using the tabular
method: F= S(0,1,2,8,10,11,14,15)
 Step 3: any two minterms which are differ from each
other by only one variable can be combined, and
unmatched variable removed.
W X Y Z
col c.
0, 2, 8, 10 _ 0 _ 0

0, 8, 2, 10 _ 0 _ 0

10 11 14, 15 1 _ 1 _
, ,

10 14 11, 15 1 _ 1 _
, ,

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 Example: simplify the Boolean function by using the tabular
method: F= S(0,1,2,8,10,11,14,15)
 Step 4: the Unchecked terms in the table form the
prime-implicants.
In col b:- w’x’y’---0,1
In col c:- x’z’—0,2,8,10and wy—10,11,14,15
The sum of prime-implicants gives the minimized function
in sum of products.

F= W’X’Y’ +X’Z’+WY

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3-9 Exclusive-OR Function
 Exclusive-OR (XOR)
 xÅy = xy'+x'y
 Exclusive-NOR (XNOR)
 (xÅy)' = xy + x'y'
 Some identities
 xÅ0 = x
 xÅ1 = x'
 xÅx = 0
 xÅx' = 1
 xÅy' = (xÅy)'
 x'Åy = (xÅy)'
 Commutative and associative
 AÅB = BÅA
 (AÅB) ÅC = AÅ (BÅC) = AÅBÅC

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Exclusive-OR Implementations
 Implementations
 (x'+y')x + (x'+y')y = xy'+x'y = xÅy

January 4, 2025 Figure 3.32 Exclusive-OR Implementations 75

Odd Function
 AÅBÅC = (AB'+A'B)C' +(AB+A'B')C =
AB'C'+A'BC'+ABC+A'B'C = S(1, 2, 4, 7)
 XOR is a odd function → an odd number of 1's, then F = 1.
 XNOR is a even function → an even number of 1's, then F = 1.

Figure 3.33 Map for a Three-variable Exclusive-OR Function

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XOR and XNOR
 Logic diagram of odd and even functions

Figure 3.34 Logic Diagram of Odd and Even Functions

January 4, 2025 77
Four-variable Exclusive-OR
function
 Four-variable Exclusive-OR function
 AÅBÅCÅD = (AB'+A'B)Å(CD'+C'D) = (AB'+A'B)(CD+C'D')+
(AB+A'B')(CD'+C'D)

Figure 3.35 Map for a Four-variable Exclusive-OR Function

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Parity Generation and Checking
 Parity Generation and Checking
 A parity bit: P = xÅyÅz
 Parity check: C = xÅyÅzÅP
 C=1: one bit error or an odd number of data bit error
 C=0: correct or an even # of data bit error

Figure 3.36 Logic Diagram of a Parity Generator and Checker

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Parity Generation and Checking

January 4, 2025 80
Parity Generation and Checking

January 4, 2025 81
 3.10 Hardware Description Language
(HDL)
 Describe the design of digital systems in a textual form
 Hardware structure
 Function/behavior
 Timing
 VHDL and Verilog HDL

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A Top-Down Design Flow

Specification

RTL design and

Simulation

Logic Synthesis

Gate Level Simulation

ASIC Layout FPGA Implementation

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Module Declaration
 Examples of keywords:
module, end-module, input, output, wire, and, or,
and not

Figure 3.37 Circuit to demonstrate an HDL

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 HDL Example 3.1
 HDL description for circuit shown in Fig. 3.37

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Gate Displays
 Example: timescale directive
 ‘timescale 1 ns/100ps

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 HDL Example 3.2
 Gate-level description with propagation delays for circuit
shown in Fig. 3.37

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 HDL Example 3.3
 Test bench for simulating the circuit with delay

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Simulation output for HDL
Example 3.3

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 Boolean Expression
 Boolean expression for the circuit of Fig. 3.37

 Boolean expression:

HDL Example 3.4

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HDL Example 3.4

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 User-Defined Primitives
 General rules:

 Declaration:

Implementing the hardware in Fig. 3.39

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 HDL Example 3.5

January 4, 2025 93
 HDL Example 3.5 Continued)

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 Figure 3.39 Schematic for circuit with_UDP_02467

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