Module 4

Introduction to Verilog
&
Verilog Data Flow Description

Dr.Zahira Tabassum
Associate Professor,
Dept of ECE,HKBKCE
 Course Objectives

• Learn different Verilog HDL constructs.

• Learn data types, operators of Verilog.
• Familiarize the different levels of abstraction
in Verilog.
 Course Outcomes

• Identify and use suitable data types and

operators to write verilog programs
• Write Verilog programs in dataflow (RTL),
• Design and verify the functionality of digital
circuit/system using test benches.
 Emergence of HDLs (Hardware Description
Languages) or Why HDL
• HDL is a CAD tool for the modern design and synthesis of
digital systems,
• Recent advances in semiconductor technology continue to
increase power and complexity, hence cannot be designed
using discrete ICs.
• They are designed using Application Specific ICs(ASICs) and
FPGAs and also require sophisticated CAD tools.
• HDL offers the designers a very efficient tool for implementing
and synthesizing designs on chips.
• Designers use HDL to describe the system in computer
language similar to several commonly used software languages
such as C.
• VHDL and Verilog are 2 commonly used HDLs.
 History of Verilog
• Gateway Design Automation developed Verilog HDL in
1983.
• It was introduced for logic simulator Verilog XL.
• Gateway was bought by Cadence in 1989 and in 1990
cadence made it publicly available.
• In 1995,Verilog HDL became IEEE standard 1364-1995.
• The language is presently maintained by Open Verilog
International Organisation.
• Verilog code structure is based on C software
Language.
 Structure of Verilog Module
• Each module must have a
🡺 module_name, which is the identifier for the module,
🡪 a module_terminal_list, which describes the input and output
terminals of the module.

Syntax of a module in Verilog

• module <module_name> (<module_terminal_list>);
...
<module internals>
...
...
endmodule

For Eg. T FF module definition:

module T_FF (q, clock, reset);
.
.
<functionality of T-flipflop>
.
.
Endmodule
 Ports
• Input: only input port, appears only on RHS of
assignment statement.
• Output: only output port, can appear on
either side of the assignment statement.
• Inout: The port can be used as both input and
output. It is bidirectional.
 Operators
• HDL has an extensive list of operators.
• Operators perform a wide variety of functions.
These functions can be classified as:
• Logical such as AND, OR, and XOR Q
• Relational to express the relation between objects. These
operators include equality, inequality, less than, less than or
equal, greater than, and greater than or equal.
• Arithmetic such as addition, subtraction, multiplication, and
division
• Shift to move the bits of an object in a certain direction, such
as right or left.
 Logical Operators
• These operators perform logical operations, such as AND,
OR, NAND, NOR, NOT, and XOR.
• The operation can be on two operands or on a single
operand.
• The operand can be single or multiple bits.
• Verilog logical operators can be classified into three
groups: Bitwise, Boolean logical, and reduction.
• The bitwise operators operate on the corresponding bits
of two operands.
Consider the statement: Z= X & Y, where the AND operator
(&) “ANDs” the corresponding bits of X and Y and stores
the result in Z.
For example, if X is the four-bit signal 1011, and Y is the four-
bit signal 1010, then Z = 1010.
Verilog Bitwise Logical Operators
Boolean logical operators.
• These operators operate on two operands, and the result is
in Boolean: 0 (false) or 1 (true).
• For example, consider the statement Z = X && Y where
&& is the Boolean logical AND operator.
• If X = 1011 and Y = 0001, then Z = 1.
• If X = 1010 and Y = 0101, then Z = 0.
• Reduction operators operate on a single operand.
• The result is in Boolean.
• For example, in the statement Y = &X, where & is
the reduction AND operator
• Assuming X = 1010, then Y = (1 & 0 & 1 & 0) = 0.
 Relational Operators
• Relational operators are implemented to compare the
values of two objects.
• The result returned by these operators is in Boolean:
false (0) or true (1).
• For the equality operator (==) and inequality operator (!=), the
result can be of type unknown (x) if any of the operands
include “don’t care,” “unknown (x),” or “high impedance z.”
Ex: if (A == B) .…….
1. If the value of A or B contains one or more “don’t care” or z
bits, the value of the expression is unknown.
2. If A is equal to B, the value of the expression is true (1).
3. If A is no equal to B, the value of the expression is false (0).

Note: If either of the operands of logical-equality (==) or logical-

inequality (!=) is X or Z, then the result will be X.
You may use case-equality operator (===) or case-inequality
operator (! ==) to match including X and Z and will always
have a known value.
Arithmetic Operators
An example of an arithmetic Verilog
operator is the addition operator (+);
The statement Y = (A + B) calculates
the value of Y as the sum of A and B.

Arithmetic Operator Precedence

 Shift and Rotate Operators
• Shift and rotate operators are implemented in many
applications, such as in multiplication and division.
• A shift left represents multiplication by two, and a shift right
represents division by two.
• Verilog has the basic shift operators.
• Shift operators are unary operators; they operate on a single
operand. To understand the function of these operators,
assume operand A is the four-bit vector 1110.
 Data Types
• Since HDL is implemented to describe the hardware of a
system, the data or operands used in the language must have
several types to match the need for describing the hardware.
• For example, if we are describing a signal, we need to specify
its type (i.e., the values that the signal can take), such as type
bit, which means that the signal can assume only 0 or 1.
• Examples of types include integer, real, vector, bit, and array.
• Verilog supports several data types including nets, registers,
vectors, integer, real, parameters, and arrays.
i. Nets
• Nets are declared by the predefined word wire.
• Nets have values that change continuously by the circuits that
are driving them.
• wire sum;
• wire S1 = 1’b0;

ii. Register
• Register, in contrast to nets, stores values until they are
updated.
• Register is declared by the predefined word reg.
Ex: reg Sum_total;

iii. Vector
• Vectors are multiple bits.
• A register or a net can be declared as a vector.
• Vectors are declared by brackets [ ].
Ex : wire [3:0] a = 4’b1010;
reg [7:0] total = 8’d12;
iv. Integers
• Integers are declared by the predefined word integer.
Ex: integer no_bits;
v. Real
• Real (floating-point) numbers are declared with the predefined
word real.
Ex: 2.4, 56.3, and 5e12.
real weight;
vi. Parameter
• Parameter represents a global constant.
• It is declared by the predefined word parameter.
Ex: module compr_genr (X, Y, xgty, xlty, xeqy);
parameter N = 3;
input [N:0] X, Y;
output xgty, xlty, xeqy;
wire [N:0] sum, Yb;
vii. Arrays
• Verilog, in contrast to VHDL, does not have a predefined word
for array.
• Registers and integers can be written as array.
Ex: reg marks [0:3];
In the above ex, marks is defined as array with four elements in
it namely marks[0], marks[1], marks[2], marks[3].
parameter N = 4;
parameter M = 3;
reg signed [M:0] carry [0:N];
In the above example carry is declared as an array of 5
elements, each element is 4 bits each.
 Styles of Descriptions
Behavioral Description
• A behavioural description models the system as to how the
outputs behave with the inputs.
• Module includes predefined word always or initial.
Data-Flow Description
• Describes how the system flows from the inputs to the
outputs.
• Description is written using boolean function of the outputs.
• Data flow statements are concurrent, their execution is
controlled by events.
Structural Description
• They model the system as components or gates.
 Data Flow description
• Signal Declaration And Assignment Statement

The boolean function y=ab+ cd

Y=s1+s2
S1=ab
S2=cd
• Input and output signals are declared in the entity as ports.
• In verilog s1 and s2 are declared as signals by using
predefined word wire.
• By default all ports are declared as wire.
• A signal assignment statement is used to assign a value to a
signal.
•The keyword assign is used for signal assignment.
 Execution of a signal assignment statement
• The execution is done in 2 phases
i. Calculation ii. Assignment.
Consider the execution of the statement
Assign 01=I1&I2;
Assign 02=I1|I2;
Let us assume T0 an event occurs causing I1=1 and I2 =1
Calculation phase: Since I1=1 and I2 =1,at T0 the value of 01 is
calculated to be 1&1=1.
•Assignment: The calculated value is assigned after a delay time. This
delay time can be implicit or explicitly specified.
•Explicit delay can be specified as assign #10 01=I1&I2;
•Value is calculated at T0 and assigned to 01 at T0 + 10 screen
units.
• If no delay specified, default a  is assigned as delay which is
very small and is not visible on the screen.
• Concurrent signal assignments
• Data flow statements are concurrent.
• All statements are executed simultaneously when an event
occurs.
• Consider an event occurs on I1 and I2 remains unchanged, as
per the example both 01 & 02 values are updated at T0 + .
• Constant declaration and assignment statements
• A constant in verilog can be declared as time or integer
depending on constant.
Ex: time period;
Period =100;
Or time period=100;
Integer k=0;
• Data Flow description of half adder
• Full adder
• Half subtractor
• Full Subtractor(from DSD Manual)
• Mux (4:1)
module mux(i,s,y);
input [3:0]i;
input [1:0]s;
output y;
assign y=(~s[1]&~s[0]&i[0])+(~s[1]&s[0]&i[1]) +
(s[1]&~s[0]&i[2])+(s[1]&s[0]&i[0]);
endmodule
 Assigning a delay time to the signal assignment
• assign #10 s1=sel & b;
2:1 mux with active low enable
Sel Gbar Y
X H L
1 L A
0 L A

Y=(G&A&~sel)+(G&B&sel) where g is invert of

Gbar.
Y=(~Gbar)&((sel&B)|(~sel&B))
Assign #21 Y=(~Gbar)&((sel&B)|(~sel&B));