Department of ECE

VLSI DESIGN
22EC2211A
Topic:

CMOS STATIC AND DYNAMIC

CHARACTERISTICS

Session - 7

CREATED BY K. VICTOR BABU

 AIM OF THE SESSION

To familiarize students with a comprehensive understanding of the fundamental principles, behavior,

and performance metrics associated with CMOS technology. .

INSTRUCTIONAL OBJECTIVES

This Session is designed to:

1. Describe the working principle of CMOS Inverter
2. Demonstrate the electrical behavior of Inverter with pull up resistive and depletion
loads.
3. Describe the Voltage Transfer Characteristic.

LEARNING OUTCOMES

At the end of this session, you should be able to:

1. Define the properties of CMOS Inverter
2. Calculation of VOH and VOL
3. Design the network/circuit using CMOS Inverters.

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 SESSION INTRODUCTION

“MOS inverter Design with various pull up Resistive & Depletion Load”

 The session starts with the introduction of the Inverter, as the nucleus of all digital designs.

 Once its operation and properties are clearly understood, designing MOS Inverter with various pull up
Resistive & Depletion Load is greatly simplified.

 The electrical behavior of these complex circuits can be almost completely derived by extrapolating the
results obtained for inverters.

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 SESSION DESCRIPTION

Introduction:

 The inverter is the most fundamental logic gate that

performs a Boolean operation on a single input variable.
 The logic symbol and the truth table of the ideal inverter
are given in figure 2.1.

 In MOS inverter circuits, both the input variable A and

the output variable B are represented by node voltages,
referenced to the ground potential. Using positive logic
convention, the Boolean (or logic) value of "1" can be
represented by a high voltage of VDD, and the Boolean
(or logic) value of "0" can be represented by a low
voltage of 0.

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 SESSION DESCRIPTION

Introduction:

 The DC voltage transfer characteristic (VTC) of the ideal

inverter circuit is shown in below figure 2.2.

 The voltage, Vth is called the inverter threshold voltage.

 Note that for any input voltage between 0 and Vth =
VDD/2, the output voltage is equal to VDD (logic “1”).
 The output switches from VDD to 0 when the input is
equal to Vth.
 For any input voltage between Vth and VDD, the output
voltage assumes a value of 0 (logic "0").
 Thus, an input voltage 0 < Vin< Vth is interpreted by this
ideal inverter as a logic "0" while an input voltage Vth
<Vin < VDD is interpreted as a logic "1".
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 SESSION DESCRIPTION

Introduction:

 An inverter circuit is a very important circuit for producing a complete

range of logic circuits.
 This is needed for restoring logic levels,
- for NAND and NOR gates, and
- for sequential and memory circuits of various forms.
• Figure 2.3 shows the generalized circuit structure of an nMOS inverter.
• The input voltage of the inverter circuit is also the gate-to-source voltage
of the nMOS transistor (Vin = VGs), while the output voltage of the
circuit is equal to the drain-to-source voltage (Vout = VDS).
• The source and the substrate terminals of the nMOS transistor, also
called the driver transistor, are connected to ground potential; hence, the
source-to-substrate voltage is VSB = 0.
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 SESSION DESCRIPTION

Voltage Transfer Characteristic (VTC)

• Applying Kirchhoff s Current Law (KCL) to this

simple circuit, we see that the load current is
always equal to the nMOS drain current.

• The voltage transfer characteristic describing V

as a function of Vin under DC conditions can
then be found by analytically solving (2.1) for
various input voltage values. The typical VTC of
a realistic nMOS inverter is shown in Figure
2.4.

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 SESSION DESCRIPTION

Resistive Load:

The basic structure of a resistive load inverter is shown in the figure 2.5.

Circuit Operation:

 When the input of the driver transistor is less than threshold voltage
VTH (Vin <VTH), driver transistor is in the cut – off region and does
not conduct any current.
 So, the voltage drop across the load resistor is ZERO and output voltage
is equal to the VDD.
 Now, when the input voltage increases further, driver transistor will
start conducting the non-zero current and nMOS goes in saturation
region.
 The various operating regions of the driver transistor and the
corresponding input-output conditions are listed in the following table.
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 SESSION DESCRIPTION

ALTERMTIVE FORMS OF PULL –UP :

Generally, the inverter circuit will have a depletion mode pull-up transistor as its load.
But there are also other configurations. Let us consider four such arrangements.

(i) Load resistance RL

(ii) nMOS depletion mode transistor pull-up

(iii) nMOS enhancement mode pull-up

(iv) Complementary transistor pull-up (CMOS)

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 SESSION DESCRIPTION

Load resistance RL:

 This arrangement consists of a load resistor as

a pull-up as shown in the figure 2.6 below.
 It consists of an nMOS transistor connected
between the output node and the ground, and
is controlled by the input voltage applied at its
gate terminal.
 A load is connected between the power supply
(VDD) and the output terminal.
 We now analyze the output voltage levels for
logic ‘0’ and logic ‘1’. Let us consider the load
as a resistor of value RL; and let the resistance

of the driver nMOS transistor be RD.

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 SESSION DESCRIPTION

Load resistance RL:

Calculation of VOH and VOL

The output voltage is expressed as follows:

For maximum VOL, we consider only the positive sign in Eqn (2.3). Therefore, the equation is rewritten as
follows:

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 SESSION DESCRIPTION

Load resistance RL:

Calculation of VIL and VIH

By definition, VIL and VIH are input voltages such that

At VIL, the nMOS transistor is in its saturation region as VDS > VGS – Vtn. Therefore, we have the following
equation:

At VIH, the nMOS transistor is in the linear region. Therefore, we have the following equation

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 SESSION DESCRIPTION

nMOS enhancement mode pull-up

• The disadvantage of a resistive inverter is that it

requires a large area on silicon in order to
implement the resistive load.
• Therefore, as an alternative to resistive load, it is
possible to design a MOS inverter with an
enhancement-type nMOS transistor acting as a load,
as shown in Fig. 2.7.

• The load nMOS transistor ML can operate both in the saturation region and in the linear region, as explained in
following: In Fig. 2.7(a), ML operates in the saturation region as its gate and drain are shorted together and tied to
the power supply, VDD. On the other hand, in Fig. 2.7(b), ML operates in the linear region depending on the bias
voltage VDD1.
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 SESSION DESCRIPTION

nMOS depletion mode transistor pull-up

 It is also possible to design an MOS inverter with a depletion-type

nMOS transistor acting as load, as shown in Fig. 2.8.
 The depletion-type nMOS transistor has a built-in channel region.
Therefore, with zero gate voltage, the nMOS is ON, whereas for large
gate voltage, the channel region gets depleted and the nMOS
transistor becomes OFF.
 In Fig. 2.8, we see that ML is always ON as its gate is shorted to the
source terminal.

 In this type of circuit, when the input is at logic low, the driver nMOS transistor MD is OFF, and the output is at
logic high through the load transistor ML. On the other hand, when the input is at logic high, the driver nMOS
transistor becomes ON, and the output is connected to the ground through MD.

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 SESSION DESCRIPTION

CMOS Inverter:

• The CMOS, or complementary MOS, inverter uses a pMOS transistor in

the pull-up network, and nMOS transistor in the pull-down network, as
illustrated in Fig. 2.9.

• When the input is at logic low, the pMOS transistor is ON, and the nMOS
transistor is OFF.

• Therefore, the output is at logic high. On the other hand, when the input is
at logic high, the pMOS transistor is OFF, and the nMOS transistor is ON,
and hence the output is at logic low.

• The advantage of a CMOS inverter is that as the nMOS and pMOS

transistors functionally complement each other, they are never ON together;
and hence, there is no direct path from VDD to the ground for static current
to flow.
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 SESSION DESCRIPTION

Voltage Transfer Characteristics:

• The VTC of a CMOS inverter are shown in Fig. 2.10. We

see that the VTC curve is divided into five different parts,
depending on the operating region of the nMOS and
pMOS transistors.

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 SESSION DESCRIPTION

Operating regions of the nMOS and pMOS transistors in

CMOS Inverter:

Region-1

 In this region the input is in the range of (0,Vtn).

 Since the input voltage is less than Vtn, the NMOS is in

cutoff region.

 No current flows from Vdd to Vss, The entire Vdd will

appear at the Output terminal.

 NMOS is in cutoff as Vgs < Vtn

 PMOS is in linear as Vgsp < Vtp and Vdsp > Vgsp -Vtp.

 Zero current flows from supply voltage and the power

dissipation is zero.
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 SESSION DESCRIPTION

Operating regions of the nMOS and pMOS transistors in

CMOS Inverter:

Region-2

 In this region the input is in the range of (Vtn,Vdd/2). Since

the input voltage is greater than Vtn the NMOS is conducting
and it jumps to saturation as it has large Vds across it (Vout is
high).

 PMOS still remains in the linear region.

 NMOS is in saturation as Vgs > Vtn and Vout >Vin - Vtn.

 PMOS is in linear region as Vdsp > Vgsp - Vtp.

 since both the transistors are conducting some amount of

current flows from supply in this.
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 SESSION DESCRIPTION

Operating regions of the nMOS and pMOS transistors in

CMOS Inverter:

Region-3
 In this region the input voltage is Vdd/2.
 At this point the output voltage is also Vdd/2 as one can see
in figure.

 At this voltage both the NMOS and PMOS are in saturation and the output drops drastically
from Vdd to Vdd/2.
 At this point a large amount of current flows from the supply. Most of the power consumed in CMOS inverter is at this
point.
 So care should be taken that the Input should not stay at Vdd/2 for more amount of time.
 NMOS is in saturation as Vgs > Vtn and Vout >Vin - Vtn.
 PMOS is in saturation as Vgsp < Vtp and Vdsp < Vgsp -Vtp.
 Large amount of current is drawn from supply and hence large power dissipation.
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 SESSION DESCRIPTION

Operating regions of the nMOS and pMOS transistors in

CMOS Inverter:

Region-4

 In this region the input voltage is in the range of (Vdd/2 , Vdd-

Vtp). Here the PMOS remains in saturation as Vout < Vin - Vtp
and Vgsp < Vtp.

 But the NMOS moves from saturation to linear region since the
drain to source voltage now is less than Vgsn-Vtn.

 NMOS is in linear as Vgs > Vtn and Vout < Vin - Vtn.

 PMOS is in saturation as Vgsp < Vtp and Vdsp < Vgsp -Vtp.

 A medium amount of current is drawn as NMOS is in linear

region and power dissipation is low.
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 SESSION DESCRIPTION

Operating regions of the nMOS and pMOS transistors in

CMOS Inverter:

Region-5
 In this region the input voltage is in the range of (Vdd-
Vtp,Vdd).
 Here the PMOS moves from saturation to cutoff as the Vgsp
is so high that Vgsp > Vtp.
 The NMOS still remains in linear as the drain to source
voltage now is less than Vgsn-Vtn.
 NMOS is in linear as Vgs > Vtn and Vout < Vin - Vtn.
 PMOS is in cutoff as Vgsp > Vtp.
 Zero current flows from the supply and so the power
dissipation is zero.

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 ACTIVITIES/ CASE STUDIES/ IMPORTANT FACTS RELATED TO THE
SESSION
Activities:
Design a network of Pull-Up to Pull-Down of an n-MOS inverter driven by another n-MOS inverter.

Articles:
a. T. F. Knight and A. Krymm, "A self-terminating low-voltage swing CMOS output driver," in IEEE
Journal of Solid-State Circuits, vol. 23, no. 2, pp. 457-464, April 1988, doi: 10.1109/4.1007.
b. T. J. Gabara and S. C. Knauer, "Digitally adjustable resistors in CMOS for high-performance
applications," in IEEE Journal of Solid-State Circuits, vol. 27, no. 8, pp. 1176-1185, Aug. 1992, doi:
10.1109/4.148326.
Case Studies:
a. CMOS Inverter: DC Analysis
(https://www.egr.msu.edu/classes/ece410/mason/files/Ch7.pdf)
b. THE CMOS INVERTER (http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter5.pdf
)

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 EXAMPLES

• These are found in mobile devices, digital cameras, home computers, cell phones, routers, network
servers, modems & virtually each other electronic device that needs logic functions.
• CMOS inverters are the most frequently used flexible MOSFET inverters that are used in designing
integrated circuits like CD4069UB CMOS hex inverter, CD4069UBE, CD40106BE, etc. They function
through very little power loss & high speed. These inverters are used for generating data in small electronic
circuits.

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 SUMMARY

The CMOS Inverter is introduced in this session with different Resistive & Depletion Load. The

enhancement and depletion modes of nMOS are also described.

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 SELF-ASSESSMENT QUESTIONS

1. Why is Inverter considered as the nucleus of all digital designs?

2. Differentiate between nMOS enhancement mode transistor pull-up and depletion mode
transistor pull-up.

3. What is the disadvantage of resistive load while implementing Inverter? Suggest any solution
to this problem.

4. Why nMOS technology is preferred more than pMOS technology?

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 TERMINAL QUESTIONS

a. What are pull-ups? Write about the resistor pull-up and its usage.
b. Derive the expression for estimation of Pull-Up to Pull-Down ratio of an n-MOS
inverter driven by another n-MOS inverter.
c. Illustrate the typical voltage transfer characteristic (VTC) of a realistic nMOS inverter.

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 REFERENCES FOR FURTHER LEARNING OF THE SESSION
Text Books:
1.Douglas A. Pucknell& Kamran Eshraghian, Basic VLSI Design, PHI, 3rd Ed., 2011
2. Neil H.E. Weste, David Harris, Ayan Banerjee, CMOS VLSI Design, A Circuits and Systems
Perspective, Pearson Education, 4th Ed., 2011
3. Sung-Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis and Design, Tata Mc-
Graw-Hill, 3rd Ed., 2003
Reference Books:
1. Jab M. Rabaey, Anantha Chandra Kasan, Borivoje Nikolic, Digital Integrated Circuits - A Design
Perspective, PHI, 2nd Ed., 2012
2. Michal John Sebastian Smith, Application-Specific Integrated Circuits, Pearson Education, 6th Ed.,
2009

Sites and Web links:

1. https://www.egr.msu.edu/classes/ece410/mason/files/Ch7.pdf
2. http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter5.pdf

3. https://nptelvideos.com/video.php?id=1317

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 THANK YOU

Team – VLSI Design

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