Computer Organization

UNIT II
INSTRUCTION DESIGN

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 SYLLABUS

Basic Computer Organization and Design:

 Instruction codes – Stored Program Organization, Indirect Address,
 Computer Registers – Common Bus Systems,
 Computer instructions – Instruction Set Completeness,
 Timing and control,
 Instruction cycle – Fetch and Decode, Determine the Type of
Instruction, Register Reference Instructions,
 Memory Reference Instructions – AND to AC, ADD to AC,
LDA :Load to AC,STA: Store AC, BUN: Branch Unconditionally,
BSA: Branch and Save Return Address, ISZ: Increment and Skip if
Zero, Control Flow Chart,
 Input Output Instructions and Interrupt – Input Output
Configuration, Input-Output Instructions, Program Interrupt,
Interrupt Cycle. 2
 Instruction Codes
• Every different processor type has its own design (different
registers, buses, microoperations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating point calculations
– The ability to pipeline several consecutive instructions to speed
execution
– Etc.

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 THE BASIC COMPUTER

• The Basic Computer has two components, a processor

and memory
• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory

• Each word is 16 bits long CPU RAM

0

15 0

4095
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 INSTRUCTIONS

• Program
– A sequence of (machine) instructions
• (Machine) Instruction
– A group of bits that tell the computer to perform a specific
operation (a sequence of micro-operation)
• The instructions of a program, along with any
needed data are stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the
instruction into the sequence of microoperations
necessary to implement it

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 STORED PROGRAM ORGANIZATION
Instruction Format
• A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for that
instruction
– An address that specifies the registers and/or locations in memory
to use for that operation
• In the Basic Computer, since the memory contains 4096 (= 212)
words, we needs 12 bit to specify which memory address this
instruction will use
• In the Basic Computer, bit 15 of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits
long, that leaves 3 bits for the instruction’s opcode
Instruction Format
15 14 12 11 0
I Opcode Address

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Addressing
mode
 ADDRESSING MODES
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the
address of the operand), (or)
– Indirect address: the address in memory of the address in memory of
the data to use
Effective Address (EA)
– The address, that can be directly used without modification to access
an operand for a computation-type instruction, or as the target address
for a branch-type instruction

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 COMPUTER REGISTERS
Registers in the Basic Computer
11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR
CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
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OUTR 8 Output Register Holds output character
 COMMON BUS SYSTEM

• The registers in the Basic Computer are connected

using a bus

• This gives a savings in circuitry over complete

connections between registers

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COMMON BUS SYSTEM
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR

PC 2

LD INR CLR

DR 3

LD INR CLR

E
ALU AC 4

LD INR CLR

INPR
IR 5

LD
TR 6

LD INR CLR
OUTR
Clock
LD 10
16-bit common bus
 COMMON BUS SYSTEM
• Three control lines, S2, S1, and S0 control which register
the bus selects as its input S S S
2 Register
1 0

00 0 x
00 1 AR
01 0 PC
01 1 DR
10 0 AC
10 1 IR
11 0 TR
11 1 Memory

• Either one of the registers will have its load signal

activated, or the memory will have its read signal
activated
– Will determine where the data from the bus gets loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto
the bus in the high order 4 bit positions
• When the 8-bit register OUTR is loaded from the bus, the
data comes from the low order 8 bits on the bus
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 COMPUTER INSTRUCTIONS

• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 -

110)
I Opcode Address
15 14 12 11
0

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 0
1 1 1 1 I/O operation
12 11

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BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol Description
I=0I=1

AND 0xxx 8xxx AND memory word to AC

1xxx 9xxx Add memory word to AC
ADD 2xxx Axxx Load AC from memory
3xxx Bxxx Store content of AC into memory
LDA 4xxx Cxxx Branch unconditionally
STA 5xxx Dxxx Branch and save return address
6xxx Exxx Increment and skip if zero
BUN

BSA
ISZ

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer
INP F800 Input character to AC 13
OUT F400 Output character from AC
SKI F200 Skip on input flag
 INSTRUCTION SET COMPLETENESS
A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function that is
known to be computable.

Instruction Types
Functional Instructions:
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions:
-Data transfers between the main memory and the processor
registers
- LDA, STA
Control Instructions:
- Program sequencing and control
- BUN, BSA, ISZ
Input / Output Instructions:
- Input and output
- INP, OUT 14
 CONTROL UNIT
• Control unit (CU) of a processor translates from machine
instructions to the control signals for the microoperations
that implement them
• Control units are implemented in one of two ways
• Hardwired Control
– CU is made up of sequential and combinational circuits to generate
the control signals

• Microprogrammed Control
– A control memory on the processor contains microprograms that
activate the necessary control signals

• We will consider a hardwired implementation of the control

unit for the Basic Computer
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 TIMING AND CONTROL
Control unit of Basic Computer

Instruction register (IR)

15 14 13 12 11 - 0 Other inputs

3x8
decoder
7654321
0
D0
I Combinational
D7 Control Control
signals
logic

T15

T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit I
sequence n
counter
(SC) c
r
e
m 16
e
n
 TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.
-- Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is
active.
D3T4: SC  0
T0 T1 T2 T3
T4 T0
Clock

T0

T1

T2

T3

T4

D3

CL R
SC
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 INSTRUCTION CYCLE
• In Basic Computer, a machine instruction is executed in the
following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction
has an indirect address
4. Execute the instruction
• After an instruction is executed, the cycle starts again at
step 1, for the next instruction

• Note: Every different processor has its own (different)

instruction cycle
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 FETCH and DECODE
• Fetch and Decode T0: AR  PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1
S2

T0
S1 Bus

S0
Memory
unit 7
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus
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DETERMINE THE TYPE OF INSTRUCTION
Start
SC  

T0
AR  PC

T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1
= 0 (Memory-reference) D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instructi
SC  0 on Execute T4
SC  memory-reference
0 instructi
on
SC 
0
D'7IT3: AR  M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr. 20
D7IT3: Execute an input-output instr.
 REGISTER REFERENCE INSTRUCTIONS
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b 0 -- b11 of IR
- Execution starts with timing signal T 3
r = D7 I T3=> Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11

r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)
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 MEMORY REFERENCE INSTRUCTIONS
Operation
Symbol Decoder Symbolic Description
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

- The effective address of the instruction is in AR and was placed there during
timing signal T 2 when I = 0, or during timing signal T 3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T 4

AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E Add to AC and store carry in E
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 Cout , SC  0
 MEMORY REFERENCE INSTRUCTIONS
LDA: Load to AC
D2T4: DR  M[AR] D2T5:
AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC 
0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return
Address
M[AR]  PC, PC  AR +
20 0 BSA 135 20 0 BSA 135
1
PC = 21 Next instruction 21 Next instruction

Memo ry, PC, AR at time T4

Memory, PC after
AR = 135execution 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory
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Memory
 MEMORY REFERENCE
INSTRUCTIONS
BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR] D6T5:
DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0)
then (PC  PC + 1), SC
0

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FLOWCHART FOR MEMORY REFERENCE
INSTRUCTIONS
Memory-reference instruction

AND ADD LDA STA

D0 T4 D1 T 4 D2 T4
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
D3 T 4 SC  0

D0 T5 D1 T 5 D2 T5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4 T4 D5 T 4 D6 T4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5 T 5 D6 T5
PC  AR DR  DR + 1
SC  0

D6 T6
M[AR]  DR
If (DR = 0)
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then (PC  PC + 1)
SC  0
 INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer

• Input-Output Configuration
Serial Computer
Input-output communication
terminal registers and
interface
flip-flops
Receiver
Printer interface FGO
OUTR

AC

Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

- The terminal sends and receives serial information

- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the 26
computer
 INPUT- OUTPUT INSTRUCTIONS

D7 IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off

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 INTERRUPT INITIATED INPUT/OUTPUT
-Open communication only when some data has to be passed
- interrupt.
- The I/O interface, instead of the CPU, monitors the I/O device.

-When the interface founds that the I/O device is ready for data
transfer, it generates an interrupt request to the CPU.

-Upon detecting an interrupt, the CPU stops momentarily the task it is

doing, branches to the service routine to process the data transfer,
and then returns to the task it was performing.

* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions
- when cleared, the computer cannot be interrupted
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 FLOWCHART FOR INTERRUPT CYCLE

- The interrupt cycle is a HW implementation of a branch and save return

address operation.
- At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch
instruction
that sends the control to an interrupt service routine
- The instruction that returns the control to the original
program is "indirect BUN 0"
 REGISTER TRANSFER OPERATIONS IN
INTERRUPT CYCLE
Memory

Before interrupt After interrupt

0 cycle 0 256
1 0 BUN 1120 PC = 1 0 BUN 1120

255 Main 255 Main

PC = 256 Program 256 Program

1120 1120
I/O I/O
Program Program

1 BUN 0 1 BUN 0

Register Transfer Statements for Interrupt Cycle

-

The fetch and decode phases of the instruction cycle

must be modified Replace T0 , T1 , T 2 with R'T0, R'T1, R'T2
- The interrupt cycle :

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