UNIT-II

8086
SYSTEM BUS STRUCTURE

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 EXTERNAL
MEMORY
ADDRESSING

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 EXTERNAL MEMORY
ADDRESSING

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 EXTERNAL MEMORY
ADDRESSING
• In 8086 the 1MB memory is physically organized as odd band

and even bank each of 512KB addressed in parallel by the

processor.
• Byte data with even address is transferred on D7-D0 bus
lines.
• Byte data with odd address is transferred on D15-D8 bus
lines.
• The processor provides 2 enable single signals BHE¯ and A0
for selection of odd and even memory banks.
• In 8-bit read from address, in even address BHE¯ remains high & in odd
address BHE¯ pulsed low.
• In 16-bit read from address, (lower byte at even address) BHE¯ pulsed low in
the first cycle in this case, since A0=0, both the low and high order memory
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banks will be selected.
 BUS CYCLES

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 BUS CYCLES
MEMORY or I/O READ FOR MINIMUM MODE

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 BUS CYCLES
MEMORY or I/O WRITE FOR MINIMUM MODE

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 SOME
IMPORTANT
COMPANION
CHIPS IN 8086
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 IMPORTANT COMPANION CHIPS

The following chips are used for the design of 8086 based system

 Clock Generator Intel 8284

 Bidirectional Bus Transceiver Intel 8286/8287

 8 Bit Input Output Port Intel 8282/8283

 Bus Controller Intel 8288 (only in MAXIMUM

mode system)

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 IMPORTANT COMPANION CHIPS
Clock Generator Intel 8284:
 Provides a stable clock

 Facility to synchronize clock signals of other 8086 MP in

case of the multiprocessor environment.

 Reset signal in synchronization with clock as required by the

8086.

 Wait state logic

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IMPORTANT COMPANION CHIPS: Clock Generator Intel 8284

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IMPORTANT COMPANION CHIPS: Clock Generator Intel 8284

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 IMPORTANT COMPANION CHIPS: Clock Generator Intel 8284
 CYSYNC: Synchronization of signals in multiprocessor environment where all
processors receive clock at EF1.
 PCLK: Clock signal output for supporting circuits.
 AEN1¯ & AEN2¯: To attribute bus priorities when both RDY1 and RDY2 are
active. 8284 responds to RDY1 when AEN1 is low , similarly RDY2 when AEN2 is
low
 RDY1: Clock frequency
 READY: Clock frequency
 RDY2: Clock frequency
 CLK: Connected to 8086/8088 CLK pin.
 RESET: Generates the Reset output as required by 8086
 RES¯: Reset logic input. External device can reset the 8086.
 OSC: Oscillator output running at crystal or EF1 frequency. Used in
multiprocessor system
 F/C¯: If high clock at EF1 is taken, If low X1,X2 is taken
 EF1: Alternate clock input
 ASYNC¯: It selects either one or two stages of synchronization for RDY1 and
RDY2 inputs. If low one level is selected. If high two levels are selected.
 X1,X2: Clock frequency
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 GND & VCC: Connects to Ground & Power
 IMPORTANT COMPANION CHIPS
Bidirectional Bus Transceiver Intel 8286/8287

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 IMPORTANT COMPANION CHIPS
Bidirectional Bus Transceiver Intel 8286/8287
 A0-A7 are connected to MP address/data bus.
 B0-B7 are connected to system bus of system.
 When T (Direction Select) is Low: data at B pins is
output via A pins
 When T (Direction Select) is High: data at A pins is
output via B pins
 8286 transfer the data unaltered while the 8287
inverts the data at the time of transfer.
 T pin is usually connected to DT/R¯ and OE¯
connected to DEN¯ of 8086.
 OE¯ must be held low for actual data transfer to take
place.
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 IMPORTANT COMPANION CHIPS
8 Bit Input Output Port Intel 8282/8283

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 IMPORTANT COMPANION CHIPS

8 Bit Input Output Port Intel 8282/8283

 8282 and 8283 are Unidirectional latch buffers
 8282 does not alter the data but 8283 inverts the
input data.
 DI0-DI7 are data inputs and DO0-DO7 are data
outputs.
 When STB (input data strobe) is high, data on
output pins track the data on input pins.
 When STB is low the data is latched and remains
unchanged.
 When OE¯ is low the data is put on output lines
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 IMPORTANT COMPANION CHIPS
Bus Controller Intel 8288

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 IMPORTANT COMPANION CHIPS

Bus Controller Intel 8288

 It is used in maximum mode configuration of 8086.

 Its main function is to decode the status line signals S0¯, S1¯,
S2¯ and to generate system bus control signals.

 It has 2 modes of operation I/O Bus mode and System Bus

mode.

 When IOB = high 8288 goes to I/O bus mode.

 When IOB = low 8288 goes to System Bus mode

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 Bus Controller Intel 8288
Effect of AEN1¯, IOB and CEN on control
signals

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 MAXIMUM
MODE BUS
CYCLE

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 8086 SYSTEM
CONFIGURATIO
N

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 MEMORY INTERFACING
 Interfacing of 8086 MP to memory is the main step in the design of
a MP based system

 The number of memory chips and the address space used

will depend on the application needs.

 Its not necessary that the address space of any MP system

should start only from zeros, it may start at any boundary of 1KB

 The diagram describes the memory address decoding using

one 74LS138 decoder

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 MEMORY INTERFACING: MEMORY ADDRESS
DECODING

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 MINIMUM
MODE SYSTEM
CONFIGURATIO
N

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 MINIMUM MODE SYSTEM CONFIGURATION

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 MINIMUM MODE SYSTEM CONFIGURATION
 In a minimum mode 8086 system, the MP 8086 is operated in
minimum mode by its MN/MX¯ pin to logic 1.
 In this all the control signals are given out by the
microprocessor itself.
 There is a single processor in the minimum mode system.
Remaining components are 8282 latches, 8286 bus
transceivers and 8284 clock generator.
 The 8282 latch is used to demultiplex the address/data bus
lines to two separate address and data buses using ALE pin.
 The 8284 clock generator provides CLK, READY and RESET
signals to the 8086.
 The data bus D0-D15 is bidirectional, in order to create a
separate data bus from address/data bus, two 8286
bidirectional bus transceivers are used. DT/R¯ and DEN¯
output of 8086 are connected to 8286 as T and OE¯
respectively
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 MAXIMUM
MODE SYSTEM
CONFIGURATIO
N

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 MAXIMUM MODE SYSTEM CONFIGURATION

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 MAXIMUM MODE SYSTEM CONFIGURATION

 In a maximum mode 8086 system, the MP 8086 is operated in

maximum mode by its MN/MX¯ pin to GND.
 In this mode there may be more than 1MP in system
configuration.
 ALE and DEN are generated by 8288 controller.
 The 8282 latch is used to demultiplex the address/data bus
lines to two separate address and data buses using ALE pin.
 The 8284 clock generator provides CLK, READY and RESET
signals to the 8086.
 The data bus D0-D15 is bidirectional, in order to create a
separate data bus from address/data bus, two 8286
bidirectional bus transceivers are used. DT/R¯ and DEN¯
output of 8086 are connected to 8286 as T and OE¯
respectively

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 INTERRUPT PROCESSING
INTERRUPT SERVICE ROUTINE (ISR)
 While the CPU is executing a program, an interrupt breaks the
normal sequence of execution of instructions, diverts its execution
to some other program. After executed ISR, the control is
transferred back again to the main program which was being
executed at the time of interruption.

 The 8086 has 4 sources of interrupts:

 Software or within-program logic

 Single step condition

 External logic as a non-maskable interrupt

 External logic as a maskable interrupt

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 DIRECT MEMORY ACCESS
(DMA)
DMA in Minimum Mode (MN/MX¯=5v):
 Two signals HOLD and HLDA are dedicated for DMA operation
 When the external logic wishes to access the memory directly, it
makes a request through high signal at HOLD pin, the 8086 samples
the HOLD input at low-to-high transition and acknowledges the
HOLD request through high-level at HLDA pin at the end of the
cycle.

DMA in Minimum Mode (MN/MX¯=GND):

 Two signals RQ¯/GT0¯ and RQ¯/GT1¯ are dedicated for DMA
operation. (RQ¯/GT0¯ has the Highest Priority)
 When the external logic wishes to access the memory
directly, it makes a request through low signal at RQ¯/GT¯
pin, the 8086 samples the RQ¯/GT¯ input at low-to-high
transition and acknowledges the DMA request at the end of
the cycle.
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