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Smitha D
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Power Electronics[21EC721]

AAT-3
Voltage control of single phase Inverter

Presented by:
Smitha D [1NC21EC017]
mitha S G[1NC21EC018]
Brundha M [1NC21EC019]
Chaithra K A [1NC21EC020]
Chaithra N [1NC21EC021]
Outline
• Introduction to Randomization and System Verilog
• Importance
• What to Randomize?
• Flow Chart
• Constraints in Randomization
• Constraints in System Verilog
• Example of Randomization in System Verilog
• Conclusion
Introduction
Randomization:
• Randomization is a technique used to introduce variability and unpredictability in
simulations
• It plays a crucial role in testing systems under a wide range of scenarios.
• Understanding randomization is essential for creating robust testbenches and
verifying designs effectively.

System Verilog:
• System Verilog is an extension of Verilog that includes advanced
features for verification.
• It provides built-in support for randomization, making it easier to
implement in testbenches.
• Understanding System Verilog is essential for leveraging its
randomization capabilities effectively.
Importance
Randomization helps to uncover corner cases that deterministic testing might miss.It enhances the
validation process by simulating real-world unpredictability. This approach increases confidence in the
design’s reliability and performance.
•Broad Test Coverage:
Randomization generates diverse input scenarios, including edge cases, ensuring thorough testing of
hardware designs.
•Stress Testing:
By pushing the system to handle unpredictable inputs, randomization helps uncover hidden bugs and
verify the design's robustness.
•Reproducibility:
Using the $random function with a fixed seed allows for repeatable tests, making it easier to debug and
resolve issues.
•Efficiency:
Automates the creation of test cases, saving time and effort in generating exhaustive input patterns
manually.
What to Randomize?
• Various parameters can be randomized
including input values, configurations,
and timing.
• Randomizing state machines can help test
different operational paths of the design.
• It is also beneficial to randomize
constraints to evaluate system behavior
under different conditions.
Flow Chart:
Constraints in Randomization:
Constraints in randomization are used to restrict the values that can be assigned to variables during the randomization
process. In Verilog, constraints are used to ensure that the randomized values meet certain conditions or requirements.

Types of Constraints:

1. Range Constraints: Used to specify a range of values for a variable.


Example: constraint c_data { data > 8'h00; data < 8'hFF; }

1. Equality Constraints: Used to specify that two or more variables have the same value.
Example: constraint c_equal { data == addr; }

Inequality Constraints: Used to specify that one variable is greater than, less than, or not equal to another variable.
Example: constraint c_inequal { data > addr; }

2. Inside Constraints: Used to specify that a variable is within a certain range or set of values.
Example: constraint c_inside { data inside {[8'h10:8'h20]}; }

Implication Constraints: Used to specify that if one condition is true, then another condition must also be true.
Example: constraint c_implication { (data > 8'h00) -> (addr > 8'h10); }
Constraints in System Verilog:
• System Verilog allows the use of
`constraint` blocks to define conditions
for random variables.

• Constraints can be used to enforce


relationships between multiple random
variables.

• They enhance the quality of


randomization by ensuring that
generated values meet specified criteria.
Example of Randomization in System Verilog

A simple example would be to create a class


with random variables and constraints.

By defining a `constraint` block, you can


control the random values generated during
simulation.

This helps to create meaningful test


scenarios that better validate the design
under various conditions.
Conclusion
• Randomization is a powerful tool for enhancing
the verification process in design testing.

• Leveraging System Verilog's capabilities allows


for efficient and effective randomization.

• By understanding what to randomize and how to


apply constraints, you can significantly improve
test coverage.
Thank You

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