MICROCONTROLLER LAB-

8051

Balaji Ramakrishna
 Prof. Cherrice Traver
MICROCONTROLLERS

Memory

Systems
ECE/CS-352: Embedded Microcontroller
CPU ROM
RAM

I/O

Subsystems:
Timers, Counters, Analog
Interfaces, I/O interfaces
A single chip
PIN DIAGRAM
COMMON MICROCONTROLLERS
•Atmel •Motorola
•ARM •8-bit
•Intel •68HC05
•8-bit •68HC08
•8XC42 •68HC11
•MCS48 •16-bit
•MCS51 •68HC12
•8xC251 •68HC16
•16-bit •32-bit
•MCS96 •683xx
•MXS296 •Texas Instruments
•National Semiconductor •TMS370
•COP8 •MSP430
•Microchip •Zilog
•12-bit instruction PIC •Z8
•14-bit instruction PIC •Z86E02
•PIC16F84
•16-bit instruction PIC
•NEC
THE NECESSARY TOOLS FOR A
MICROPROCESSOR/CONTROLLE
R
 CPU: Central Processing Unit
 I/O: Input /Output
 Bus: Address bus & Data bus
 Memory: RAM & ROM
 Timer
 Interrupt
 Serial Port
 Parallel Port
MICROCONTROLLER ARCHITECTURES
Memory
0
Address Bus
Program
CPU Data Bus + Data Von Neumann
2n
Architecture
Memory
0
Address Bus
Program
CPU Fetch Bus Harvard
Address Bus 0
Architecture
Data Bus Data
“ORIGINAL” 8051 MICROCONTROLLER
Oscillator 4096 Bytes 128 Bytes Two 16 Bit
and timing Program Data Timer/Event
Memory Memory Counters

8051 Internal data bus

CPU

64 K Byte Programmable Programmable

Bus I/O Serial Port Full
Expansion Duplex UART
Control Synchronous
subsystem interrupts
Shifter

External interrupts Control Parallel ports Serial Output

Address Data Bus Serial Input
I/O pins
8051 ARCHITECTURE
 RAM memory space allocation in the 8051

7FH

Scratch pad RAM

30H

2FH
Bit-Addressable RAM

20H
1FH Register Bank 3
18H
17H
Register Bank 2
10H
0FH Register Bank 1 )Stack(
08H
07H
Register Bank 0
00H
 Memory space
BIT ADDRESSABLE RAM

Figure 2-
6
Summary
of the
8051 on-
chip data
memory
(RAM)
BIT ADDRESSABLE RAM
PROGRAM STATUS WORD (PSW)
ACCESSING EXTERNAL
DATA MEMORY
ACCESSING EXTERNAL
CODE MEMORY
INTERFACING WITH EXTERNAL ROM
EXTERNAL MEMORY
EXTERNAL MEMORY TIMING DIAGRAM
THE EA' (EXTERNAL ACCESS) PIN IS USED TO CONTROL THE
INTERNAL OR EXTERNAL MEMORY ACCESS.
THE SIGNAL 0 IS FOR EXTERNAL MEMORY ACCESS AND
SIGNAL 1 FOR INTERNAL MEMORY ACCESS.
THE PSEN' (PROGRAM STORE ENABLE) IS FOR READING
EXTERNAL CODE MEMORY WHEN IT IS LOW (0) AND EA IS
ALSO 0.
THE ALE (ADDRESS LATCH ENABLE) ACTIVATES THE PORT 0
JOINED WITH PORT 2 TO PROVIDE 16 BIT EXTERNAL
ADDRESS BUS TO ACCESS THE EXTERNAL MEMORY. THE ALE
MULTIPLEXES THE P0:
ALE=1 FOR LATCHING ADDRESS ON P0 AS A0-A7 IN THE
16 BIT ADDRESS BUSS, ALE=0 FOR LATCHING P0 AS DATA I/O.
P0.X IS NAMED ADX BECAUSE P0 IS MULTIPLEXED FOR
ADDRESS BUS AND DATA BUS AT DIFFERENT CLOCK TIME.
WR' PROVIDES THE SIGNAL TO WRITE EXTERNAL DATA
MEMORY
RD' PROVIDES THE SIGNAL TO READ EXTERNAL DATA AND
CODE MEMORY.
ACCESSING ROM USING INDEXED
ADDRESSING
INDEXED ADDRESSING
PORT 0
PORT1
PORT 2
PORT3
 There are 4 8-bit ports: P0, P1, P2 and P3. All of them are dual
purpose ports except P1 which is only used for I/O. The following
diagram shows a single bit in an 8051 I/O port.
When a program writes a one byte value to a port or a single bit value
to a bit of a port, assigning the value to the port as follows:
P1 = 0x12; or P1^2=1;
P1 represents the 8 bits of port 1 and P1^2 is the pin #2 of the port 1
of 8051 defined in the reg51.h of C51, a C dedicated for 8051 family.
When data is written to the port pin, it first appears on the latch input
(D) and is then passed through to the output (Q) and through an
inverter to the Field Effect Transistor (FET).
If you write a logic 0 to the port pin(DFF Q=0), it is inverted to logic 1
and turns on the FET gate. It makes the port pin connected to ground
(logic 0).
If logic 1 is written to the port pin(DFF Q=1), , then it is inverted to a
logic 0 and turns off the FET gate. Therefore the pin is at logic 1
because it is connected to high.
 PORT P1 (Pins 1 to 8): The port P1 is a port dedicated for general
I/O purpose. The other ports P0, P2 and P3 have dual roles in
addition to their basic I/O function.
 PORT P0 (pins 32 to 39): When the external memory access is

required then Port P0 is multiplexed for address bus and data

bus that can be used to access external memory in conjunction
with port P2. P0 acts as A0-A7 in address bus and D0-D7 for port
data. It can be used for general purpose I/O if no external
memory presents.
 PORT P2 (pins 21 to 28): Similar to P0, the port P2 can also play a

role (A8-A15) in the address bus in conjunction with PORT P0 to

access external memory.
 PORT P3 (Pins 10 to 17):
In addition to acting as a normal I/O port,
 P3.0 can be used for serial receive input pin(RXD)
 P3.1 can be used for serial transmit output pin(TXD)
in a serial port,
 P3.2 and P3.3 can be used as external interrupt
pins(INT0’ and INT1’),
 P3.4 and P3.5 are used for external counter input
pins(T0 and T1),
 P3.6 and P3.7 can be used as external data memory
write and read control signal pins(WR’ and RD’)read
and write pins for memory access.