Unit II - MOS Introduction

MOS Transistors
 MOS Transistor Physical Structure

 The above image shows the N channel MOSFET transistor physical structure with its four
terminals: Gate, Drain, Source and Substrate. Normally the Source and the substrate are
connected together.
 The Gate with W and L dimensions is separated from the substrate by a dielectric (SiO 2),
creating a similar structure of the capacitor plates.
 If a positive voltage is applied to the gate, negative charges are induced (inversion
layer) on the substrate surface and they create a conduction path between the Drain
and Source terminals.
 The minimum voltage needed to create the inversion layer is called threshold voltage
(VT). This is a characteristic feature of the transistor.
 If VGS < VT, the drain-source current is zero. Typical values for this voltage are between
0.5 and 3 volts.
 Types of MOS Transistors

FIGURE : nMOS transistor (a) and pMOS transistor (b)

 Types of MOS Transistor
1. Enhancement mode Transistor - the Channel which is NOT existing is Created between
Drain and Source with application of Gate-Source Voltage
 nMOS Enhancement mode
 pMOS Enhancement mode

2. Depletion mode Transistor - In depletion mode the already existing Channel width
between Drain and source is reduced with application of Gate - Source Voltage
 nMOS Depletion mode
 pMOS Depletion mode
 Circuit Symbols for MOS Transistor

If the fourth terminal is not shown, it is assumed that the body is connected to
the appropriate supply.
 MOS structure demonstrating - Accumulation, Depletion and
Inversion

 A negative voltage is applied to the gate, so there is

negative charge on the gate.
 The mobile positively charged holes are attracted to
the region beneath the gate. This is called the
accumulation mode.

 A small positive voltage is applied to the gate, resulting

in some positive charge on the gate.
 The holes in the body are repelled from the region
directly beneath the gate, resulting in a depletion
region forming below the gate.

 A higher positive potential exceeding a critical

threshold voltage Vt is applied, attracting more
positive charge to the gate.
 The holes are repelled further and some free electrons
in the body are attracted to the region beneath the
The threshold voltage depends on the number of dopants gate.
in the body and the thickness tox of the oxide.  This conductive layer of electrons in the p-type body is
It is usually positive,
called the inversion layer.
 MOS Transistor Demonstrating – Cut-off Region, Linear Region &
Saturation Region
1. Cut-off Region : ( )

 The transistor consists of the MOS stack between two n-type regions called the source
and drain. The inversion layer / channel is formed as , but there is no current flow as
Vds = 0V.
 We say the transistor is OFF, and this mode of operation is called cutoff.
 It is often convenient to approximate the current through an OFF transistor as zero,
especially incomparison to the current through an ON transistor.
 However, that small amounts of current leaking through OFF transistors can become
significant, especially when multiplied by millions or billions of transistors on a chip.
 2.. Non-saturation Region: ()

 Assume now that VGS > VT and that a small voltage, VDS, is
applied between drain and source.
 The voltage difference causes a current ID to flow from drain
to source
 Using a simple analysis, a first-order expression of the
current as a function of VGS and VDS can be obtained.
 At a point x along the channel, the voltage is V(x), and the gate-to-channel voltage at that
point equals VGS – V(x). Under the assumption that this voltage exceeds the threshold
voltage all along the channel, the induced channel charge per unit area at point x can be
computed as .
 The magnitude of current increases linearly with increasing drain voltage till a
particular drain voltage determined by the following relations :
VGS ≥ Vth and VDS < Vsat = VGS – Vth
 The magnitude of current is the charge flowing through the channel and the time
taken to drift across the channel.

𝑄 𝑐h𝑎𝑛𝑛𝑒𝑙 𝐶h𝑎𝑟𝑔𝑒 𝑓𝑙𝑜𝑤𝑖𝑛𝑔 𝑡h𝑟𝑜𝑢𝑔h 𝑡h𝑒 𝑐h𝑎𝑛𝑛𝑒𝑙

𝐼 𝑑𝑠 = = −−− −( 1)
𝑡 𝑡𝑖𝑚𝑒 𝑡𝑎𝑘𝑒𝑛 𝑡𝑜 𝑑𝑟𝑖𝑓𝑡 𝑎𝑐𝑜𝑟𝑠𝑠 𝑡h𝑒 𝑐h𝑎𝑛𝑛𝑒𝑙
2. Non-saturation Region(Cont.)
T

𝑪𝒉𝒂𝒓𝒈𝒆 𝒇𝒍𝒐𝒘𝒊𝒏𝒈𝒕𝒉𝒓𝒐𝒖𝒈𝒉 𝒕𝒉𝒆𝒄𝒉𝒂𝒏𝒏𝒆𝒍

𝑄 𝑐h𝑎𝑛𝑛𝑒𝑙 =𝐶 𝑔 𝑉 − − − − ( 3 )
𝑤h𝑒𝑟𝑒, 𝐶 𝑔 − 𝑔𝑎𝑡𝑒𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑎𝑛𝑐𝑒 ,𝑉 −𝑎𝑝𝑝𝑙𝑖𝑒𝑑 𝑉𝑑𝑠 𝑓𝑜𝑟 𝑡h𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑓𝑙𝑜𝑤

(
𝑄 𝑐h𝑎𝑛𝑛𝑒𝑙 =𝐶 𝑔 𝑉 𝑔𝑠 − 𝑉 𝑡 −
1
2
𝑉
)
𝑑𝑠
− −−−( 4)

𝑤h𝑒𝑟𝑒𝑉 𝑔𝑠 −𝑉 𝑡 𝑖𝑠 𝑡h𝑒 𝑒𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒 𝑣𝑜𝑙𝑡𝑎𝑔𝑒

𝑇h𝑒𝑚𝑎𝑔𝑛𝑖𝑡𝑢𝑑𝑒 𝑜𝑓 𝑡h𝑒 𝑑𝑟𝑎𝑖𝑛 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑖𝑛𝑛𝑜𝑛− 𝑠𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛𝑟𝑒𝑔𝑖𝑜𝑛𝑖𝑠 𝑔𝑖𝑣𝑒𝑛𝑏𝑦(1)
2. Non-saturation Region(Cont.)

𝜀 𝐴
2
𝜀 𝑜𝑥 W . L
( )
𝐼𝑛 𝑒𝑞𝑢𝑎𝑡𝑖𝑜𝑛 5 𝑤h𝑒𝑟𝑒 𝐶 𝑔 = = − − − − (6)
𝑑 𝑡 𝑜𝑥
𝑆𝑢𝑏𝑠𝑡𝑖𝑡𝑢𝑡𝑖𝑛𝑔 ( 6 ) 𝑖𝑛 ( 5 ) , 𝐼 𝑑𝑠 𝑖𝑠𝑔𝑖𝑣𝑒𝑛 𝑎𝑠

( ) −− −( 7)
𝜀 𝑜𝑥 W . L 1
𝑉 𝑔𝑠 − 𝑉 𝑡 − 𝑉
𝑡 𝑜𝑥 2 𝑑𝑠
𝐼 𝑑𝑠 = 2
𝐿
𝜇 𝑛 𝑉 𝑑𝑠

𝑻𝒉𝒆𝒓𝒆𝒇𝒐𝒓𝒆 ,
; VGS ≥ Vth and VDS < Vsat = VGS – Vth
 3.Saturation Region

 As the value of the drain-source voltage is further increased, the assumption that the
channel voltage is larger than the threshold all along the channel ceases to hold. This
happens when VGS - V(x) < VT.
 At that point, the induced charge is zero, and the conducting channel disappears or is
pinched off.

( )
Beyond a certain point , the surface concentrationis like ln
𝑛𝑠
𝑛𝐵
𝑎𝑛𝑑 𝑡h𝑒𝑟𝑒𝑓𝑜𝑟𝑒 𝑠𝑡𝑜𝑝 𝑖𝑛𝑐𝑟𝑒𝑎𝑠𝑖𝑛𝑔
𝑎𝑛𝑑 𝑡h𝑒 𝑠𝑢𝑟𝑓𝑎𝑐𝑒 𝑝𝑜𝑡𝑒𝑛𝑡𝑖𝑎𝑙𝑖𝑠 𝑝𝑖𝑛𝑛𝑒𝑑𝑜𝑓𝑓 𝑤h𝑒𝑛 𝑛𝑠 ≅ 𝑁 𝐴
𝑤h𝑒𝑟𝑒 , 𝑠𝑢𝑟𝑓𝑎𝑐𝑒 𝑝𝑜𝑡𝑒𝑛𝑡𝑖𝑎𝑙 ,𝜓 𝑠=
𝐾𝑇
𝑞
ln
( )
𝑛𝑠
𝑛𝐵
3.Saturation Region (Cont.)

𝑺𝒖𝒃𝒔𝒕𝒊𝒕𝒖𝒕𝒆 𝑽 𝒅𝒔 =𝑽 𝒈𝒔 − 𝑽 𝒕 𝒊𝒏 𝒆𝒒𝒖𝒂𝒕𝒊𝒐𝒏( 𝟖)

(
𝑰 𝒅𝒔 = 𝜷 𝑽 𝒈𝒔 − 𝑽 𝒕 −
𝟏
𝟐 )
( 𝑽 𝒈𝒔 − 𝑽 𝒕 ) 𝑽 𝒈𝒔 − 𝑽 𝒕

( )
𝟐
[ 𝑽 𝒈𝒔 − 𝑽 𝒕 ]
𝑰 𝒅𝒔 =𝜷
𝟐

--- (9)
 MOS Transistor Demonstrating – Cut-off Region, Linear
Region & Saturation Region

= ; Linear Region