Chapter 5

Central Processing Unit(CPU)

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 5.1 Instruction Formats

Instruction sets are differentiated by the following features:

• Number of bits allowed per instruction.(16, 32,and 64bits)
• Number of explicit operands per instruction.((zero, one,
two, and three being the most common)
• Operand storage in the CPU (data can be stored in a stack
structure or in registers)
• Operand location (register-to-register, register to-memory
or memory-to-memory, which simply refer to the
combinations of operands allowed per instruction)
• Types of operations.
• Type and size of operands. (can be addresses, numbers, or
even characters). 2
 Cont….

In designing an instruction set, consideration is given to:

• Instruction length.
 Whether short, long, or variable.
• Number of operands.
• Number of addressable registers.
• Memory organization.
 Whether byte- or word addressable.
• Addressing modes.
 Choose any or all: direct, indirect or indexed.

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 Cont….

• Most computers fall into one of the three types of CPU X = Operand Address

organizations:
1. Single Accumulator (AC) Organization, i.e. ADD X AC  AC  M [ X ]
2. General register Organization, ADD R1,R2,R3 R1  R2  R3
-Register organization show how registers are selected and how
data flow between register and ALU. A decoder is used to select a
particular register.
3. Stack Organization, i.e. : PUSH X TOS  M [ X ] no address field if
the instruction is ADD/MUL
 A stack cannot be accessed randomly.

In choosing one over the other, the tradeoffs are simplicity (and cost)
of hardware design with execution speed and ease of use.
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 Cont….

Stack Organization
Stack or LIFO(Last-In, First-Out)
• A storage device that stores information.
 The item stored last is the first item retrieved = a stack of tray.
• Stack Pointer (SP)
 The register that holds the address for the stack
 SP always points at the top item in the stack
• Two Operations of a stack : Insertion and Deletion of
Items
 PUSH : Push-Down = Insertion
 POP : Pop-Up = Deletion

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 Cont….

Stack
1) Register Stack
 a finite number of memory words or register(stand alone)
2) Memory Stack Address

 a portion of a large memory 64

1. Register Stack FU LL E MTY

PUSH
4
SP = 0, SP  SP  1 : Increment SP SP C
B
3
2
EMTY = 1,
FULL = 0 M [ SP ]  DR : Write to the stack Last Item
A 1
0
If ( SP 0) then ( FULL  1) : Check if stack is full

EMTY  0 : Mark not empty DR

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 Cont….

• The first item is stored at address 1, and the last item is stored at
address 0 : Read item from the top of stack
DR  M [ SP ] Address
POP : SP  SP  1 : Decrement Stack Pointer
Memory unit
1000
PC
If ( SP 0) then ( EMTY  1) : Check if stack is empty Program
(instruc tions)
FULL  0 : Mark not full
2000
AR
Data

2. Memory Stack (operands)

3000
PUSH SP  SP  1 Stac k

M [ SP ]  DR 3997
SP 3998
•The first item is stored at address 4000 3999
4000

POP : DR  M [ SP ] Start Here 4001

SP  SP  1 DR
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 Cont….

• We are accustomed to writing expressions using infix

notation, such as: Z = X + Y.
• Stack arithmetic requires that we use postfix notation: Z =
XY+.
 This is also called reverse Polish notation, (somewhat)
in honor of its Polish inventor, Jan Lukasiewicz (1878 -
1956).

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 Cont….

RPN (Reverse Polish Notation)

Common arithmetic expressions written in infix notation (A*B + C *D)
• The difficulties when evaluated by a computer
• A stack organization is very effective for evaluating
arithmetic expressions.
• A * B + C * D  AB * CD * +
( 3 * 4 ) + ( 5 * 6 )  34 * 56 * +

4 5 5 30

3 3 12 12 12 12 42

3 4 * 5 6 * +

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 Cont….

The influence of the number of addresses on computer instruction

X = (A + B)*(C + D) with zero, one, two or three
address instructions
•In Zero-Address ISA
PUSH A

PUSH B
TOS  A
TOS  B
ADD TOS  ( A  B )
PUSH C TOS  C
TOS  D
PUSH D
TOS  (C  D )
ADD TOS  (C  D )  ( A  B )
M [ X ]  TOS
MUL
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POP X
 Cont….

 Stack-organized computer does not use an address field for the instructions
ADD, and MUL
 PUSH, and POP instructions need an address field to specify the operand
 Zero-Address : absence of address ( ADD, MUL )
• In a one-address ISA, like MARIE, the infix expression,
X = (A + B) ∗ (C + D) is:
LOAD A AC ← M [A]
ADD B AC ← AC + M [B]
STORE T M [T] ← AC
LOAD C AC ← M [C]
ADD D AC ← AC + M [D]
MUL T AC ← AC ∗ M [T]
STORE X M [X] ← AC
* All operations are done between the AC register and memory operand
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 Cont….

• In a two-address ISA, (e.g.,Intel, Motorola), the infix

expression,
X = (A + B) ∗ (C + D)
might look like this:
MOV R1, A R1 ← M [A]
ADD R1, B R1 ← R1 + M [B]
MOV R2, C R2 ← M [C]
ADD R2, D R2 ← R2 + M [D]
MUL R1, R2 R1 ← R1∗R2
MOV X, R1 M [X] ← R1
• Computers with multiple processor registers use the move
instruction with a mnemonic MOV to symbolize a transfer 12
instruction.
 Cont….

• With a three-address ISA, (e.g.,mainframes), the infix

expression,
X = (A + B) ∗ (C + D)
might look like this:

ADD R1, A, B R1 ← M [A] + M [B]

ADD R2, C, D R2 ← M [C] + M [D]
MUL X, R1, R2 M [X] ← R1 ∗ R2
• The advantage of the three-address format is that it results in
short programs when evaluating arithmetic expressions.
• Note that as we reduce the number of operands allowed per
instruction, the number of instructions required to execute the
desired code increases. 13
 Cont….

• We have seen how instruction length is affected by the

number of operands supported by the ISA.
• In any instruction set, not all instructions require the same
number of operands.
• Operations that require no operands, such as HALT,
necessarily waste some space when fixed-length
instructions are used.
• One way to recover some of this space is to use expanding
opcodes.

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 Cont….

• MARIE uses a fixed length instruction with a 4-bit

opcode and a 12-bit operand. Instructions on current
architectures can be formatted in two ways:
• Fixed length—Wastes space but is fast and results
in better performance when instruction-level
pipelining is used.
• Variable length—More complex to decode but
saves storage space.

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 5.2 Instruction types
Instructions fall into several broad categories that you
should be familiar with:
• Data movement (e.g. load, store, Push, Pop..)
• Arithmetic
• Boolean
• Bit manipulation - used for setting and resetting
individual bits within a given data word.
e.g. Shift left, shift right, rotate left, rotate right
• I/O- (The basic schemes for handling I/O are
programmed I/O, interrupt-driven I/O)
• Control instructions(e.g. SKIPCOND)
• Special purpose instructions(e.g flag control, and cache
management.) 16
 5.3 Addressing Modes

• The way the operands are chosen during program execution

is dependent on the addressing mode of the instruction.
• The addressing mode specifies a rule for interpreting or
modifying the address field of the instruction before the
operand is actually referenced.
• They can specify a register, or a memory location.
• The actual location of an operand is its effective address.
• Certain addressing modes allow us to determine the address
of an operand dynamically.

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 Cont….

• Immediate addressing is where the data is part of the instruction.

• an immediate mode instruction has an operand field rather than
an address field.
• Direct addressing is where the address of the data is given in the
instruction.
• Register addressing is where the data is located in a register.
• Indirect addressing In this mode, the bits in the address field
specify a memory address that is to be used as a pointer. The
effective address of the operand is found by going to this
memory address
• Register indirect addressing uses a register to store the address
of the data.
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 Cont….

• Indexed addressing uses a register (implicitly or explicitly) as an

offset, which is added to the address part of the instruction to
determine the effective address of the data.
• For example, if the operand X of the instruction Load X is to be
addressed using indexed addressing, assuming R1 is the index
register and holds the value 1, the effective address of the operand
is actually X + 1.
• In stack addressing the operand is assumed to be on top of the
stack.

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 Cont….

• There are many variations to these addressing modes

including:
 Base addressing
 Indirect indexed.
 Base/offset.
 Self-relative
 Auto increment - decrement.

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 Example: For the instruction shown, what value is loaded into
the accumulator for each addressing mode?

800

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 Example: For the instruction shown, what value is loaded into
the accumulator for each addressing mode?

800

900

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 Example: For the instruction shown, what value is loaded into
the accumulator for each addressing mode?

800

900

1000

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 Example: For the instruction shown, what value is loaded into
the accumulator for each addressing mode?

800 + 800 = 1600

800
900

1000
700

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Characteristics of RISC and CISC
• Complex Instruction Set Computer(CISC)
(e.g. Intel Architecture)
Major characteristics of a CISC architecture
 A large number of instructions - typically from 100
to 250 instructions.
 It is a CPU design plan based on single
commands, which are skilled in executing
multi-step operations.
 CISC computers have small programs. It has a
huge number of compound instructions, which
takes a long time to perform.
 It has a memory unit to implement complex 25
instructions.
 Cont….

Reduced Instruction Set Computer (RISC) around 1980’s.

(e.g. Pentium ,MIPS)
Major characteristics of a RISC architecture
 A reduced instruction set computer is a computer which only
uses simple commands that can be divided into several
instructions which achieve low-level operation within a single
CLK cycle.
 every instruction is expected to attain very small jobs. In this
machine, the instruction sets are modest and simple,
 Relatively few instructions
 All operations done within the registers of the CPU
 Hardwired rather than microprogrammed control
 Execution time is very less 26