COMPUTER

ORGANIZATI
ON AND
ARCHITECTU
RE (COA)
Ms. Umang Kant
AP, KIET, CSE-AIML Department
Ph.D Research Scholar, DTU,
CSE
)
CONTENTS
1. Types of Microoperations
1. Register Transfer Microoperations
2. Arithmetic Microoperations
3. Logical Microoperations
4. Shift Microoperations

2. Arithmetic Logic Shift Unit

 UNIT 01
INTRODUCTI
ON
TYPES OF
MICROOPERATIONS
Type of Description Example
Microoperat
ions
Register • Transfer binary information from one register R2R1
Transfer to another.
Microoperat • Do not change the information content when
ions the binary information moves from one
(Refer Slide register to destination register.
1.4)
Arithmetic • Perform arithmetic operation on numeric R3R1+R2
Microoperat data stored in registers. R3R1+R2’+1
ions • Change the information content during the
transfer.
Logical • Perform bit manipulation operations on data
Microoperat stored in registers.
ions • Change the information content during the
REGISTER TRANSFER
MICROOPERATIONS
 Refer to Previous Slides (1.3 and 1.4 Unit1)
ARITHMETIC
MICROOPERATIONS
 The basic arithmetic microoperations are: addition, subtraction, increment,
decrement, shift etc.
 The arithmetic microoperation defined by the statement below specifies the
add microoperation: R3R1+R2. It states that the content of R1 are added to
contents of R2 and sum is transferred to R3. To implement this statement,
hardware requires 3 registers and digital component that performs addition.
 Subtraction is most often implemented through complementation and
addition.
 The subtract operation is specified by the following statement:
R3R1+R2’+1. Instead of writing the minus operator it as R3R1-R2, we
can write it as written above. R2’ is the symbol for 1’s complement of R2.
Adding 1 to 1’s complement produces 2’s complement. Adding the contents
of R1to 2’s complement of R2 is equivalent to R1-R2.
1’S & 2’S COMPLEMENT OF
BINARY INFORMATION
 1’s Compliment
To get 1's complement of a binary number, simply invert the given
number. For example, 1's complement of binary number 110010
is 001101.
 2’s Compliment
To get 2’s complement of a binary number, simply invert the given
number and add 1 to the least significant bit (LSB) of given result.
SHORTCUT to find 2’s Compliment
1. Write down the given number.
2. Starting from LSB, copy all the 0s till the first 1.
3. Copy the 1st 1.
4. Compliment the remaining bits.
 ADDER-COMBINATION LOGIC
CIRCUIT
Half Adder Full Adder
A Half-adder circuit needs two binary Full Adder circuit needs three binary
inputs and two binary outputs. (AND & inputs and two binary outputs. (AND,
EX-OR Gates) EX-OR & OR Gates)
The input variable shows the augend The input variable shows the augend,
and addend bits whereas the output addend and carry from previous circuit
variable produces the sum (S) and carry (Cin). bits whereas the output variable
(Cout). produces the sum (S) and carry (Cout).
The truth table for a half-adder is The truth table for a full-adder is
'x' and 'y' are the two inputs, and S Two of the input variable 'x' and 'y',
(Sum) and C (Carry) are the two represent the two significant bits to be
outputs. added. The third input variable 'z',
The simplified sum of products (SOP) represents the carry from the previous
expressions is: lower significant position. The outputs
S = x'y+xy', C = xy are designated by the symbol 'S' for
sum and 'C' for carry.
The block and logic diagram for a half- The logic diagram for a full-adder circuit
adder circuit can be represented as: can be represented as:
BINARY ADDER
 Digital circuit that forms the arithmetic sum of two bits and previous
carry is called Full Adder.
 Digital circuit that generates the arithmetic sum of two binary
numbers of any lengths is called Binary Adder.
 The figure shows the interconnection of four full adders to provide a
4-bit binary adder.
 The augend bits of A and the addend bits of B are designated by
subscript numbers from right to left, with subscript 0 denoting the low
order bit.
 The carries are connected in a chain through the full adders. The
input carry to the binary adder is C0 and the output carry is C4. The S
outputs of the full adders generate the required sum bits.
BINARY ADDER-
SUBTRACTOR

 The addition and subtraction operations can be combined into one

common circuit by including an exclusive-OR gate with each full adder.
 A 4-bit adder-subtractor is shown in the figure.
 The mode input M controls the operation. When M=0, the circuit is an
adder and when M=1 the circuit becomes a subtractor.
 Each EX-OR gate receives input M and one of the inputs of B.
 When M=0, we have B EX-OR 0 = B. The full adders receive the value
B, the input carry is 0, and circuit performs A sum B.
 When M=1, we have B EX-OR 1 = B’ and C0= 1.
 The B inputs are all complemented and a 1 is added through the input
carry.
 The circuit performs the operation A plus the 2’s compliment of B.
BINARY INCREMENTER

 The increment microoperation adds one to the number in a register.

 For example, if a 4-bit register has a binary value 0110, it will go to
0111 after it is incremented.
 This can be accomplished by means of half-adders connected in
cascade.
 The figure shows a 4-bit combinational circuit incrementor.
 One of the inputs to the least significant half adder is connected to
logic 1 and the other input is connected to the least significant bit of the
number to be incremented.
 The output carry from one half adder is connected to one of the inputs
of the next-higher-order half adder.
 The circuit receives the four bits from A0 through A3, adds one to it,
BINARY INCREMENTER
 The output carry C4 will be 1 only after incrementing 1111. This
also causes outputs S0 to S3 to go to 0.
 The circuit shown in the figure can be extended to an n-bit binary
incrementer by extending the diagram to include n half adders.
 The least significant bit must have one input connected to logic 1.
The other inputs receive the number to be incremented or the carry
from the previous stage.
ARITHMETIC
CIRCUIT
 The basic component of an
arithmetic circuit is the parallel
adder.
 By controlling the data inputs
to the adder, it is possible to
obtain different types of
arithmetic operations.
 The diagram of a 4-bit
arithmetic circuit is shown in the
figure. It has four full-adder
circuits that constitute the 4-bit
adder and four multiplexers for
choosing different operations.
 ARITHMETIC
CIRCUIT
There are 4-bits inputs A and B and a 4-bit output D.
 The four inputs from A go directly to the X inputs of
the binary adder.
 Each of the four inputs from B are connected to the
data inputs of the multiplexers.
 The multiplexers data inputs also receive the
complement of B.
 The other two data inputs are connected to logic-0
and logic-1.
 The four multiplexers are controlled by two
selection inputs S1 and S0.
 The input carry Cin goes to the carry input of the S1 S2 Y
full adder in the least significant position. The other 0 0 B
carries are connected from one stage to the next.
0 1 B’
By controlling the value of Y with the two selection
inputs S1 and S0 and making Cin to 0 or 1, it is 1 0 0
possible to generate the eight arithmetic 1 1 1
microoperations.
ARITHMETIC CIRCUIT
1. Addition 2. Subtraction
 When S1S0=00, the value of B is  When S1S0=01, the complement
applied to the Y inputs of the of B (B’) is applied to the Y inputs
adder. of the adder.
 If Cin=0, the output D= A+B.  If Cin=1, then D=A+B’+1. This
 If Cin=1, the output D= A+B+1 produces A plus the 2’s
 Both cases perform the add compliment of B, which is
microoperation with or without equivalent to subtraction of A-B.
adding the input carry (Cin).  If Cin=0, then D=A+B’. This
equivalent to a subtract with
borrow, i.e. A+B’

3. Increment 4. Decrement
 When S1S0=10, the inputs from  When S1S0=11, the inputs from
B are neglected, and all 0’s are B are neglected, and all 1’s are
inserted into the Y inputs. Here, inserted into the Y inputs.
D=A+0+Cin.  If Cin=0, D=A-1 which is the
 If Cin=0, D=A. It refers to the decrement operation. This is
direct transfer from input A to because a number with all 1’s is
output D. equal to the 2’s compliment of 1.
LOGIC
MICROOPERATIONS
 Logic microoperations specify binary operations for strings of bits
stored in registers.
 These microoperations consider each bit of the register separately
and treat them as binary variables.
 For example, the EX-OR microoperation with the contents of two
registers R1 and R2 is symbolized by the statement .
It specifies a logic microoperation to be executed on the individual bits
of the registers R1 and R2 provided that the control variable P=1.
 We have a total of 16 microoperations, which can be performed on
two binary variables.
 These 16 microoperations can be determined from all possible truth
tables obtained with two binary variables as shown in the figure.
LOGIC
MICROOPERATI
ONS
 The 16 logic
microoperations are derived
from these functions by
replacing variable x by the
binary content of register A
and variable y by the binary
content of register B.
The 16 logic microoperations
listed in the second column
represent the relationship
between the binary content of
two registers A and B.
 LOGIC MICROOPERATIONS
HARDWARE

IMPLEMENTATION
The hardware implementation of logic
microoperations requires that logic gates be inserted
for each bit or pair of bits in the registers to perform
the required logic function.
 Although there are 16 logic microoperations, most
computer systems use only four gates-AND, OR, EX-
OR, and NOT, from which other logic functions can be
derived.
 Figure shows one stage of a circuit that generates
the four basic logic microoperations.
 It consists of four gates and a multiplexer. Each of
the four logic operations is generated through a gate
that performs the required logic.
 The outputs of the gates are applied to the data
inputs of the multiplexer.
 The two selection inputs S1S0 choose one of the
data inputs of the multiplexer and direct its value to
the output.
 1. Selective Set
 This operation sets to 1 the

LOGIC MICROOPERATIONS bits in register A where

there are corresponding 1’s
in register B.
APPLICATIONS  It does not affect bit
positions of A that have 0’s
in register B.
 Logic microoperations are very  The OR microoperation can
useful for manipulating individual be used to selectively set
bits or a portion of a word stored bits of register.
in a register. Example:
 They can be used to change bit
values, delete a group of bits or
insert new bit values into a 2. Selective Compliment
register.  This operation complements
 The following examples show bits in A where there are
how the bits of one register corresponding 1’s in B.
(designated by A) are manipulated  It does not affect bit
by logic microoperations as a positions of A that have 0’s
function of the bits of another in register B.
register (designated by B).  The Ex-OR microoperation
can be used to perform this
operation.
LOGIC MICROOPERATIONS
APPLICATIONS
3. Selective Clear 5. Insert
 This operation clears to 0 the bits  This operation inserts a new
of A only where there are value into a group of bits.
corresponding 1’s in B.  This is done by first masking the
 AND microoperation is used to bits and then Oring them with
implement this operation. the required value.
 The corresponding  For example, suppose register A
microoperation is AA. contains 8 bits 0110 1010. To
 Example replace the four left most bits by
the value 1001 we first mask the
4 unwanted bits and then insert
the new values.
 The mask operation is an AND
microoperation and insert
operation is an OR
microoperation.
4. Mask STEP1 Masking
 This operation is similar to the
selective-clear operation except
that the bits of A are cleared only
when there are corresponding 0’s
in B. STEP2 Inserting
LOGIC MICROOPERATIONS
APPLICATIONS
6. Clear
 The clear operation compares the words in A and B and produces an all
0’s result if the two numbers are equal.
 This operation is achieved by EX-OR microoperation.
 Example:
SHIFT MICROOPERATIONS

 Shift microoperations are used for serial transfer of data.

 The contents of a register can be shifted to the left or the right.
 During the shift-left operation, the serial input transfers a bit into
the rightmost position.
 During the shift-right operation, the serial input transfers a bit
into the leftmost position.
 There are three types of shifts: logical, circular and
arithmetic.
 The symbolic notation for the shift microoperations is shown in
the table.
LOGICAL SHIFT
 A logical shift is one that transfers 0 through the
serial input.
 The symbols shl and shr for logical shift-left and
shift-right microoperations.
 These microoperations specify a 1-bit shift to the left
of the content of register R and a 1-bit shift to the right
of the content of register R.
 The bit transferred to the end position through the
serial input is assumed to be 0 during a logical shift.
 In shl, MSB is lost and in shr, LSB is lost. Hence there
is loss of information in logical shift.
 Do it yourself, (i) 1101 shl 3 (ii) 1010 1101 shr 1
CIRCULAR SHIFT
 The circular shift, also known as rotate operation,
circulates the bits of the register around the two
ends without loss of information.
 This is accomplished by connecting the serial
output of the shift register to its serial input.
 We will use the symbols cil and cir for the circular
shift left and right, respectively.
 In cil, MSB becomes the LSB, and in cir, LSB
becomes the MSB.
 Do it yourself: 1001 1000 cil and cir
ARITHMETIC
SHIFT
 An arithmetic shift is a
microoperation that shifts a signed
binary number to the left or right.
 An arithmetic shift left (asl)
multiplies a signed binary number by
2. It is similar to logical shift left
microoperation.
 An arithmetic shift right (asr)
divides a signed binary number by 2.
 Arithmetic shift must leave the
signed bit unchanged because the
sign of the number remains the same
when it is multiplied or divided by 2.
 Do it yourself: (i) 0000 1010 by 2
HARDWARE
IMPLEMENTATIO
NA combinational circuit shifter
 can be
constructed with multiplexers as shown in
the figure.
 The 4 bit shifter has 4 data inputs, A0
through A3, and four data outputs, H0
through H3.
 There are two serial inputs, one for shift left
(IL) and shift right (IR).
 When the selection input S=0, the input
data are shifted right, whereas when S=1,
the input data are shifted left.
 The function table in the figure shows which
input goes to each output after the shift.
 A shifter with n data inputs and outputs
requires n multiplexers.
 The two serial inputs can be controlled by
another multiplexer to provide the three
possible types of shifts.
ARITHMETIC LOGIC SHIFT
UNIT
 Instead of having individual registers performing the
microoperations directly, computer systems employ a number of
storage registers connected to a common operational unit called an
arithmetic logic unit (ALU).
 ALU is a combinational circuit so that the entire register transfer
operation from the source registers through the ALU and into the
destination register can be performed during one clock pulse period.
 The shift microoperations are often performed in a separate unit,
but sometimes the shift unit is made part of the overall ALU.
 The arithmetic, logic and shift circuits introduced in previous
sections can be combined into one ALU with common selection
variables.
 One stage of an arithmetic logic shift unit is shown in the figure.
ARITHMETIC
LOGIC SHIFT
UNIT
 Particular
microoperation is selected
with inputs S1 and S0.
 A 4x1 multiplexer at the output
chooses between an arithmetic
output in Di and logic output in Ei.
 The data in the multiplexer are
selected with inputs S3 and S2. The
other two data inputs to the
multiplexer receive inputs Ai-1 for the
shift right operations and Ai+1 for
the shift left operations.
 The circuit whose one stage is
specified in the figure, provides eight
arithmetic microoperations, four logic
operations, and two shift operations.
 Each operations is selected with the
five variables S3, S2, S1, S0, and Cin.
Cin is used for selecting and
arithmetic operations only.
 ARITHMETIC
LOGIC SHIFT
UNIT
The table lists 14 operations of the
ALU.
 The first 8 are arithmetic operations
and are selected with S3S2=00.
 The next 4 are logic operations and
are selected with S3S2=01.
 The input carry has no effect during
the logic operations and is marked
with don’t care x’s.
 The last 2 operations are shift
operations and are selected with
S3S2=10 and 11.
 The other 3 selection inputs have
no effect on the shift.