EC464: LOW POWER VLSI

Module-1
Physics of Power dissipation in MOSFET devices
Need for low power circuit design, MIS Structure, Short channel
effects-surface scattering, punch through, velocity saturation,
impact ionization Hot electron effects, Drain Induced Barrier
Lowering, Deep submicron transistor design issues.
 Need for low power design
 To continue to improve the performance of the circuits and to integrate more functions
into each chip, feature size has to continue to shrink. As a result the magnitude of power
per unit area is growing and the accompanying problem of heat removal and cooling is
worsening. Examples are the general-purpose microprocessors. Even with the scaling
down of the supply voltage from 5 to 3.3 and then 3.3 to 2.5 V, power dissipation has not
come down.
 Portable battery-powered applications of the past were characterized by low
computational requirement. The last few years have seen the emergence of portable
applications that require processing power up until now. Two vanguards of these new
applications are the notebook computer and the digital personal communication services
(PCSs). People are beginning to expect to have access to same computing power,
information resources, and communication abilities when they are traveling as they do
when they are at their desk.
 Low-power design is not only needed for portable applications but also to reduce the
power of high-performance systems. With large integration density and improved speed
of operation, systems with high clock frequencies are emerging. These systems are using
high-speed products such as microprocessors. The cost associated with packaging,
cooling and fans required by these systems to remove the heat is increasing significantly.
 Need for low power design
 A representative of what the very near future holds is the portable multimedia
terminal. Such terminals will accept voice input as well as hand-written (with a
special pen on a touch-sensitive surface) input. Unfortunately, with the technology
available today, effective speech or hand-writing recognition requires significant
amounts of space and power. For example, a full board and 20 W of power are
required to realize a 20,000-word dictation vocabulary. Conventional nickel—
cadmium battery technology only provides a 26 W of power for each pound of
weight. Once again, advances in the area of low-power microelectronics are
required to make the vision of the inexpensive and portable multimedia terminal a
reality.
 Another issue related to high power dissipation is reliability. With
the generation of on-chip high temperature, failure mechanisms
are provoked. They may include silicon interconnect fatigue,
package related failure, electrical parameter shift etc.
 Minimizing power consumption calls for conscious effort at each abstraction
level and at each phase of the design process.
Physics of Power dissipation in MOSFET devices

Figure 1 The MIS structure

 Figure 1 shows the MIS structure. A layer of thickness d of insulating material is
sandwiched between a metal plate and the semiconductor substrate.
 Let us assume the semiconductor be of p -type. A voltage V is applied between
the metal plate and the substrate. Let us first consider the case when V = 0. As we are
considering an ideal MIS diode, the energy difference , between the metal work
function and the semi- conductor work function is zero, that is,

 'The work function is defined as the minimum energy necessary for a metal electron
in a metal—vacuum system to escape into the vacuum from an initial energy at the
Fermi level.
 The electron affinity of a semiconductor is the difference in potential between
an electron at the vacuum level and an electron at the bottom of the conduction
band
In an ideal MIS diode the insulator has infinite
resistance and does not have either mobile charge carriers Intrinsic Fermi level
or charge centers.  In intrinsic semiconductor
As a result, the Fermi level in the metal lines up with the , the number of holes in
Fermi level in the semiconductor. valence band is equal to
The Fermi level in the metal itself is same throughout the number of electrons in
(consequence of the assumption of uniform doping). the conduction band.
This is called the flat-band condition as in the energy 
band diagram, the energy levels and , appear as straight Hence, the probability of
lines (Figure 2) occupation of energy
levels in conduction band
and valence band are
equal.
 Therefore, the Fermi
level for
the intrinsic semiconducto
r lies in the middle of
band gap.

Figure 2 Energy bands in an unbiased MIS diode.

 When the voltage V is negative, the holes in the p-type semiconductor are attracted
to and accumulate at the semiconductor surface in contact with the insulator layer.
Therefore this condition is called accumulation.
 In the absence of a current flow, the carriers in the semiconductor are in a state of
equilibrium and the Fermi level appears as a straight line. The Maxwell—
Boltzmann statistics relates the equilibrium hole concentration to the intrinsic
Fermi level:

 So the intrinsic Fermi level has a higher value at the surface than at a
point deep in the substrate and the energy levels and , bend upward near
the surface (Figure 3). The Fermi level E F in the semiconductor is now
— qV below the Fermi level in the metal gate.

Figure 3 Energy bands

when a negative bias is applied.
• When the applied voltage V is positive but small, the holes in the p-type
semiconductor are repelled away from the surface and leave negatively charged
acceptor ions behind.
• A depletion region, extending from the surface into the semiconductor, is created.
This is the depletion condition. Besides repelling the holes, the positive voltage on
the gate attracts electrons in the semiconductor to the surface. The surface is said
to have begun to get inserted from the original p-type to n-type.
• While V is small, the concentration of holes is still larger than the concentration of
electrons. This is the weak-inversion condition and is important to the study of
power dissipation in MOSFET circuits. The bands at this stage bend downward
near the surface (Figure 4).

Figure 4Energy bands when a small positive bias is applied.

 If the applied voltage is increased sufficiently, the bands bend far enough that level
Ei ; at the surface crosses over to the other side of level EF .
 When V is increased to the extent that the electron density at the surface n,
becomes greater than the hole density in the bulk, onset of strong inversion
is said to have occurred. This condition is depicted in Figure 5.

Figure 5 Energy bands in strong inversion

 The various modes depending upon the applied voltage can be summarized
as,

 V=0, flat band condition

 V= -ve, Accumulation
 V=small +ve, weak inversion
 V=large +ve, stronger inversion
 Threshold Voltage
 n-type MOS: Majority carriers are electrons.
 p-type MOS: Majority carriers are holes.
 Positive/negative voltage applied to the gate (with respect to substrate)
 enhances the number of electrons/holes in the channel and increases conductivity
between source and drain.
 Vt defines the voltage at which a MOS transistor begins to conduct.
 For voltages less than Vt (threshold voltage), the channel is cut off.
 In normal operation, a positive voltage applied between source and drain (Vds).
 No current flows between source and drain (Ids = 0) with Vgs = 0 because of back to
back pn junctions.
 For n-MOS, with Vgs > Vtn, electric fi eld attracts electrons creating channel.
 Channel is p-type silicon which is inverted to n-type by the electrons attracted by the
electric field.
• Three modes based on the magnitude of Vgs: accumulation,
depletion and inversion.
 Operating regions
 What are the parameters that effect the magnitude of Ids?

 The distance between source and drain (channel length).

 The channel width.
 The threshold voltage.
 The thickness of the gate oxide layer.
 The dielectric constant of the gate insulator.
 The carrier (electron or hole) mobility.

 The important regions of operation of MOSFET are:

 Cut-off: accumulation, Ids is essentially zero.
 Nonsaturated: weak inversion, Ids dependent on both Vgs
and Vds.
 Saturated: strong inversion, Ids is ideally independent of
Vds.
 Threshold Voltage
 Vt is also an important parameter. What effects its value?

 The parameters that effect Vt include:

 The gate conductor material (poly vs. metal).
 The gate insulation material (SiO2).
 The thickness of the gate material.
 The channel doping concentration.

 However, Vt is also dependent on

 Vsb (the voltage between source and substrate), which is normally 0 in digital devices.
 Temperature: changes by -2mV/degree C for low substrate doping levels.
 Body effect
 Assume that Vs=Vd=0 and Vg<Vth, so that a
depletion region is formed under the gate as shown
in fig. (a).
 When, Vb more –ve, more holes will be attracted
by the bulk potential (Vb), leaving behind large
negative charge behind.
 As a result the depletion region becomes wider as
shown in fig. (b).
 Threshold voltage is a function of total charge in
the depletion region
 The gate charge must mirror the depletion charge
Qd.
 So as Qd increases, the gate charge should increase
and for that the gate potential has to be increased.
This results in increase in threshold voltage.
 This phenomenon is known as body effect.
 With body effect,
 =+γ
 The body effect coefficient, γ = /
 is the source –bulk surface potential
 Short channel effects
 The main drives for reducing the size of the transistors, i.e.,
their lengths, is increasing speed and reducing cost.
 When we make circuits smaller, their capacitance reduces,
thereby increasing operating speed.
 However, when the device size is reduced further, it may result
in unwanted side effects and these are called short channel
effects. These effects are
 Surface scattering,
 Punch through,
 Velocity saturation,
 Impact ionization
 Hot electron effects,
 Drain induced barrier lowering,
 Narrow width effects
 Surface scattering
 The velocity of the charge carriers is defined by the mobility of that carrier
times the electric field along the channel. That is.
v= μE
 When the carriers travel along the channel, they are attracted to the surface by
the electric field created by the gate voltage.
 As a result, they keep crashing and bouncing against the surface, during their
travel, following a zig-zagging path.
 This effectively reduces the surface mobility of the carriers, in comparison with
their bulk mobility.
 The change in carrier mobility impacts the current-voltage relationship of
the transistor
 As the length of the channel becomes shorter, the lateral electric field
created by becomes stronger.
 To compensate that, the vertical electric field created by the gate voltage
needs to increase proportionally, which can be achieved by reducing the
oxide thickness.
 As a side effect, surface scattering becomes heavier, reducing the effective
mobility in comparison with longer channel technology nodes.
 DIBL (Drain Induced Barrier Lowering)
 Drain-induced barrier lowering (DIBL) is a short-channel
effect in MOSFETs referring originally to a reduction of threshold voltage of
the transistor at higher drain voltages.
 The source and drain depletion regions can intrude into the channel even
without bias, as these junctions are brought closer together in short channel
devices.
 This effect is called charge sharing since the source and drain in effect take
part of the channel charge, which would otherwise be controlled by the gate.
 As the drain depletion region continues to increase with the bias, it can
actually interact with the source to channel junction and hence lowers the
potential barrier.
 This problem is known as Drain Induced Barrier Lowering (DIBL).
 When the source junction barrier is reduced, electrons are easily injected into
the channel and the gate voltage has no longer any control over the drain
current.
As channel length decreases, the barrier φB to be surmounted by an
electron from the source on its way to the drain reduces
 Drain Punch Through

 When the drain is at high enough voltage with respect to the source, the
depletion region around the drain may extend to the source, causing current
to flow irrespective of gate voltage (i.e. even if gate voltage is zero).
 This is known as Drain Punch Through condition and the punch through
voltage VPT given by:

 So when channel length L decreases (i.e. short channel length case), punch
through voltage rapidly decreases.
 Impact ionization
 In short channel devices, the effect of electric field will be higher.
 High electric field increases the velocity of electrons.
 These electrons impact the drain, and electron –hole pairs will be generated.
 Hot electron effect
 The hot electron effect is due to the shrinking of technology.
 If we go on reducing the length of the gate, the electric field at the drain of
the transistor increases (for a fixed drain voltage).
 The field may become so high that electrons are imparted with enough
energy to become what is termed as "hot".
 These electrons impact the drain, and electron–hole pairs will be generated.
 The electrons enter gate oxide, it will cause gate current.
 This may lead to the degradation of device parameters like threshold
current, subthreshold current, and transconductance.
 The holes enter the substrate and they will cause a substrate current
The deposition of negative charge on the gate may increase threshold
voltage by increasing flat band voltage.
This effect is usually limited to n-channel devices as holes have much
lower mobility than electrons and the barrier between the valence band of
oxide and silicon is higher at about 5eV compared to 3 eV between the
conduction band of silicon and oxide

Methods to reduce the hot electron effect

1. Reduce the supply voltage.

2. Use STI(Shallow trench isolation).
3. Hot carrier effects are less problematic for holes in p-MOSFETs.
4. LDD (lightly doped drain) can be a solution for the stress of the
hot carrier effect.
5. Use a long-channel device.
 Velocity Saturation
 Velocity saturation occurs in any general solid state device when charged
carriers move in a solid under the force of an electric field, they acquire a
velocity proportional to the magnitude of this electric field.
 This applied electric field (E) and the carrier velocity (v) are related through
the mobility parameter μ.
v= μE
 For small electric field, μ is constant and independent of the applied electric
field.
μ= (constant)
 As a result when carrier velocity is plotted versus the applied electric field,
the result is a straight line
 Both the electron and hole drift velocities saturate at applied electric fields
in excess of about 100 kV/cm.
 In short-channel devices, the electric field near the drain can attain values in
excess to 400kV/cm.
Figure :Electric field versus Carrier velocity in a solid
 Where EC is the critical electric field, EY is the channel field, α has a value
close to 2 for electrons and 1 for holes.
 Velocity saturation will yield an Ids(sat) value smaller than that predicted is
ideal relation ,and it will yield a smaller Vds(sat) value that predicted .
 In a short channel MOSFET before attaining pinch off carrier drift velocity
saturates and thus the current saturation occurs at a low value of Vds.
 Ids will be linear with Vgs.
 Thus the short-channel devices therefore experience an extended saturation
region, and tend to operate more often in saturation conditions than their long-
channel counterparts.
 Narrow width effect
 Another related effect in MOSFETs is the narrow width effect, where the VT goes
up as the channel width Z is reduced for very narrow devices.
 This can be understood from Fig. given below, where some of the depletion
charges under the LOCOS isolation regions have field lines electrically
terminating on the gate.
 Unlike the SCE(Short channel effect), where the effective depletion charge is
reduced due to charge sharing with the source/drain, here the depletion charge
belonging to the gate is increased.
 The effect is not important for very wide devices, but becomes quite important as
the widths are reduced below 1μm.
 Deep submicron devices design issues
 Scaling down feature size is an important issue for high-performance and
high-density circuits.
 However, some second order effects become serious for short-channel
devices.
 The reduction of short channel effect (SCE), has become a major challenge
in deep sub-micrometer devices and circuits.

 The important SCE includes,

 Threshold voltage roll-off and
 Drain induced barrier lowering (DIBL),
 Short-channel threshold voltage roll-off
• Fig.6 shows a schematic of a MOS transistor. Here L is the channel length and Xj
is the source and drain junction depth

Fig.6 A schematic of a MOS transistor.

• The surface potentials of short channel and long channel devices before strong
inversion are shown in fig.7. The drain, source and body voltages are all zero.

Fig.7 The surface potentials of short channel and long channel devices (Vd=0V)
 For a long channel transistor, the barrier is constant.
 As for a short channel device, the barrier is reduced along with the scaling
of the channel length.
 Therefore, the smaller the channel length, the lower the threshold voltage.
 The relationship between threshold voltage and transistor channel length is
shown in fig. 8

Fig.8 Threshold voltage versus channel length. In order to make the device work properly,
dVth/dL cannot be too large. This will determine the minimum channel length (Lmin)
 Drain-induced barrier lowering
• Fig. 9 shows the surface potentials of long-channel and short-channel
devices at a large drain voltage (Vd).
• For a long-channel device, the barrier is not sensitive to Vd. However, the
barrier of a short-channel device will reduce along with the increase of
drain voltage, which will cause a higher subthreshold current and lower
threshold voltage.

Fig. 9 The surface potentials of short channel and long channel devices (Vd > 0V)
 Minimizing short channel effect
• In order to minimize a short-channel effect, a sufficient large aspect ratio (AR) of the
device is required. AR is defined as,

AR=DIMENSION lateral/ DIMENSION vertical (1)

For a MOSFET, AR can be expressed as

Where and are the silicon and oxide permittivities

• L, , d, are channel length, gate oxide thickness, depletion depth and junction depth
respectively.
• From the above equation, we can see that reducing d and will reduce the SCE of a
MOSFET. In order to minimize SCE, a modified MOSFET structure can be used.
• Fig. 10 shows the low-impurity channel shallow-junction MOSFET
 Fig.10 Low-impurity channel shallow-junction MOSFET

 The small SCE of this transistor is because of the small depletion depth and
junction depth.
 The AR of a single gate silicon-on-insulator (SOI) MOSFET is shown in
fig.11.
• Since d , the AR is given by

Fig.11 A single-gate SOI MOSFET

  Fig. 12 shows a double-gate silicon-on-insulator (DGSOI) MOSFET. The AR of
DGSOI MOSFET is

Fig.12 A DGSOI MOSFET

 It is clear that the effective junction depth and the depletion width are reduced to half of
that of a bulk MOSFET.
 Therefore, the SCE of a DGSOI MOSFET is much smaller than a bilk silicon MOSFET,
which makes it a good candidate for deep sub micrometer applications.
 Short channel threshold voltage roll-off and DIBL are two short-channel effects, which will
complicate the transistor operation