Amritsar College of Engineering & Technology, Amritsar, Punjab, INDIA

NAAC - A grade, NBA accredited courses(2009-12, 2016-18), UGC Autonomous College

SUBJECT: Computer Architecture

TOPIC: Input-Output of BC, Interrupt initiated IO
Design of Basic Computer & AC

Er. Pavitar Singh

Assistant Professor
Department of Computer Science and
Engineering

1 Er. Pavitar Singh [email protected] CSE 3 rd Sem COALP

 OBJECTIVES

After going through this topic, you should be able to:

• Know how input-output terminals send & receive information;

• Understand interrupt initiated IO with flowchart;
• Learn the design of Basic computer.

Er. Pavitar Singh [email protected] CSE 3 rd Sem CA

2
Input-Output of basic computer
Input-Output Serial Computer
terminal communicati registers and
on interface flip-flop
FGO

Receiver
Printer OUTR
Interface

INPR Input register - 8 bits

OUTR Output register - 8 bits
FGI Input flag - 1 bit AC
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

Transmitter
Keyboard INPR
Interface

FGI
Er. Pavitar Singh [email protected] CSE 3 rd Sem CA
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 Input-Output of basic computer
 A computer can serve no useful purpose unless it communicates with
the external environment.
 To exhibit the most basic requirements for input and output
communication, we will use a terminal unit with a keyboard and
printer.
 The terminal sends and receives serial information and each quantity of
information has eight bits of an alphanumeric code.
 The serial information from the keyboard is shifted into the input
register INPR.
 The serial information for the printer is stored in the output register
OUTR.
 These two registers communicate with a communication interface
serially and with the AC in parallel.

Er. Pavitar Singh [email protected] CSE 3 rd Sem CA

4
 Process of input information transfer
 Initially, the input flag FGI is cleared to 0. When a key is struck in the
keyboard, an 8-bit alphanumeric code is shifted into INPR and the
input flag FGI is set to 1.
 As long as the flag is set, the information in INPR cannot be changed
by striking another key. The computer checks the flag bit; if it is 1, the
information from INPR is transferred in parallel into AC and FGI is
cleared to 0.
 Once the flag is cleared, new information can be shifted into INPR by
striking another key.

Er. Pavitar Singh [email protected] CSE 3 rd Sem CA

5
 Process of outputting information
 The output register OUTR works similarly but the direction of
information flow is reversed.
 Initially, the output flag FGO is set to 1. The computer checks the flag
bit; if it is 1, the information from AC is transferred in parallel to
OUTR and FGO is cleared to 0. The output device accepts the coded
information, prints the corresponding character, and when the operation
is completed, it sets FGO to 1.
 The computer does not load a new character into OUTR when FGO is
0 because this condition indicates that the output device is in the
process of printing the character.

Er. Pavitar Singh [email protected] CSE 3 rd Sem CA

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 INTERRUPT INITIATED INPUT/OUTPUT
- Open communication only when some data has to be passed --> interrupt.

- The I/O interface, instead of the CPU, monitors the I/O device.

- When the interface founds that the I/O device is ready for data transfer, it
generates an interrupt request to the CPU

- Upon detecting an interrupt, the CPU stops momentarily the task it is

doing, branches to the service routine to process the data transfer, and then
returns to the task it was performing.

* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions

- when cleared, the computer cannot be interrupted

Er. Pavitar Singh [email protected] CSE 3 rd Sem CA

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 FLOWCHART FOR INTERRUPT CYCLE
R = Interrupt f/f
Instruction cycle =0 =1 Interrupt cycle
R

Fetch and decode Store return address

instructions in location 0
M[0]  PC

Execute =0
IEN
instructions
=1 Branch to location 1
PC  1
=1
FGI
=0
=1 IEN  0
FGO R0
=0
R1

- The interrupt cycle is a HW implementation of a branch and save return address

operation.
- At the beginning of the next instruction cycle, the instruction that is read from
memory is in address 1.
- At memory address 1, the programmer must store a branch instruction that
sends the control to an interrupt service routine
- The instruction that returns the control to the original program is "indirect BUN
0"
 REGISTER TRANSFER OPERATIONS IN INTERRUPT
CYCLE
Memory
Before interrupt After interrupt cycle
0 0 256
1 0 BUN 1120 PC = 1 0 BUN 1120

Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program

1 BUN 0 1 BUN 0

Register Transfer Statements for Interrupt Cycle

- R F/F  1 if IEN (FGI + FGO)T0T1T2
 T0T1T2 (IEN)(FGI + FGO): R 
1

- The fetch and decode phases of the instruction cycle

must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
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Er. Pavitar Singh [email protected] CSE 3 rd Sem CA
RT2: PC  PC + 1, IEN  0, R  0, SC  0
 Design of Basic Computer

DESIGN OF BASIC COMPUTER(BC)

Hardware Components of BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops(Status):
I, S, E, R, IEN, FGI, and FGO
Decoders: a 3x8 Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC

Control Logic Gates

- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit

10 Er. Pavitar Singh [email protected] CSE 3 rd Sem CA

 Description
COMPLETE COMPUTER DESCRIPTION
Flowchart of Operations
start
SC  0, IEN  0, R  0

=0(Instruction =1(Interrupt
R
Cycle) Cycle)
R’T0 RT0
AR  PC AR  0, TR  PC
R’T1 RT1
IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0
R’T2 RT2
AR  IR(0~11), I  IR(15) PC  PC + 1, IEN  0
D0...D7  Decode IR(12 ~ 14) R  0, SC  0

=1(Register or I/O) =0(Memory Ref)

D7

=1 (I/O) =0 (Register) =1(Indir) =0(Dir)

I I

D7IT3 D 7I’T3 D7’IT3 D 7’I’T3

Execute Execute AR <- M[AR] Idle
I/O RR
Instruction Instruction
Execute MR D7’T4
Instruction

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 Description
COMPLETE COMPUTER DESCRIPTION
Microoperations

Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
Indirect AR  M[AR]
D7IT3:
Interrupt
T0T1T2(IEN)(FGI + FGO): R1
AR  0, TR  PC
RT0: M[AR]  TR, PC  0
RT1: PC  PC + 1, IEN  0, R  0, SC  0
Memory-ReferenceRT2:
AND DR  M[AR]
D0T4: AC  AC  DR, SC  0
ADD D0T5: DR  M[AR]
D1T4: AC  AC + DR, E  Cout, SC  0
LDA DR  M[AR]
D1T5:
AC  DR, SC  0
STA D2T4:
M[AR]  AC, SC  0
BUN D2T5: PC  AR, SC  0
BSA D3T4: M[AR]  PC, AR  AR + 1
D4T4: PC  AR, SC  0
ISZ D5T4: DR  M[AR]
D5T5: DR  DR + 1
D6T4: M[AR]  DR, if(DR=0) then (PC  PC + 1),
D6T5: SC  0
D6T6:
12 Er. Pavitar Singh [email protected] CSE 3 rd Sem CA
 Description
COMPLETE COMPUTER DESCRIPTION
Microoperations

Register-Reference
D7IT3 = r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC  0
CLA AC  0
rB11:
CLE E0
CMA rB10:
AC  AC
CME rB9: E  E
CIR rB8: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB7: AC  shl AC, AC(0)  E, E  AC(15)
INC rB6: AC  AC + 1
SPA rB5: If(AC(15) =0) then (PC  PC + 1)
SNA rB4: If(AC(15) =1) then (PC  PC + 1)
SZA If(AC = 0) then (PC  PC + 1)
SZE rB3:
If(E=0) then (PC  PC + 1)
HLT rB2: S0
rB1:
Input-Output rB0: (Common to all input-output instructions)
(i = 6,7,8,9,10,11)
D7IT3 = p SC  0
INP IR(i) = Bi AC(0-7)  INPR, FGI  0
OUT p: OUTR  AC(0-7), FGO  0
SKI pB11: If(FGI=1) then (PC  PC + 1)
SKO If(FGO=1) then (PC  PC + 1)
ION pB10:
IEN  1
IOF pB9: IEN  0
pB8:
13 pB7:
Er. Pavitar Singh [email protected] CSE 3 rd Sem CA
pB6: