FUNCTIONAL BLOCKS OF A COMPUTER

FUNCTIONAL BLOCKS OF A COMPUTER

INPUT UNIT
OUTPUT UNIT
 MEMORY UNIT
• Store programs and data
• Two classes of storage
Primary storage
Fast
Programs must be stored in memory while they are being
executed
Large number of semiconductor storage cells
Processed in words
Address
RAM and memory access time
Memory hierarchy – cache, main memory
Secondary storage – larger and cheaper
MEMORY REPRESENTATION

M=2^n*y

n=No of address lines

Y=No of data lines
MEMORY UNIT
SECONDARY STORAGE
ALU
CONTROL UNIT
 TIMING & CONTROL

• The timing for all registers in the basic computer is

controlled by A MASTER CLOCK GENERATOR.
• The clock pulses are applied to all flip-flops and
registers in the system, including the flip-flops and
registers in the control unit.
• The clock pulses DO NOT CHANGE THE STATE of a
register unless the register is enabled by a control
signal (i.e., Load).
• The control signals are generated in the control unit
and provide :
• control inputs for the multiplexers in the common bus,
• control inputs in processor registers, and
• microoperations for the accumulator.

• There are two major types of control organization:

1.Hardwired control
2.Microprogrammed control
• In the Hardwired Organization,
• the control logic is implemented with gates, flip-flops,
decoders, and other digital circuits.
• Adv: produces fast mode operation.
• Disadv: requires changes in the wiring among various
components if design has to be modified.
• In the Microprogrammed Organization,
• the control information is stored in a control memory
• The control memory is programmed to initiate the
required sequence of microoperations.
• Adv: microprogram in control memory has to be updated,
if design has to be modified.
 CONTROL UNIT for the BASIC COMPUTER
Instruction Register (IR)
CU consists of 15 14 13 12 11 - 0 Other inputs
•Two decoders
•A sequence counter 3x8
•No.of control logic gates decoder
7 6543 210
D0
I Control
D7 Control
logic outputs
gates
T15
T0

15 14 . . . . 2 1 0
4 x 16
Sequence decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock
• Inputs to the control unit come from IR (an
instruction read from the memory).
• A hardwired control is implemented in basic
computer using:
• A 3 X 8 decoder to decode opcode bits 12-14 into signals
D0, ..., D7.
• A 4-bit binary sequence counter (SC) to count from 0 to 15
to achieve time sequencing.
• A 4 X 16 decoder to decode the output of the counter into
16 timing signals, T0, ..., T15.
• A flip-flop (I) to store the addressing mode bit in IR.
• A digital circuit (Control Logic gates) with
• Inputs : D0, ..., D7, T0, ..., T15, I, and address bits (11-0) in
IR—to generate control outputs supplied to control inputs
and select signals of the registers and the bus
REGISTERS
List of Registers for the Basic Computer
Register Number Register Register
symbol of bits name Function

DR 16 Data register Holds memory operands

AR 12 Address register Holds address for memory

AC 16 Accumulator Processor register

IR 16 Instruction register Holds instruction code

PC 12 Program counter Holds address of instruction

TR 16 Temporary register Holds temporary data
INPR 8 Input register Holds input character
OUTR 8 Output register Holds output character
11 0
Basic Computer PC

Registers and memory 11

AR
0
Memory

15 0 4096 x 16
IR
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC
 COMMON BUS SYSTEM
• The basic computer has
• eight registers
• a memory unit
• a control unit
• Paths must be provided to transfer information from
one register to another and between memory and
registers.
• To avoid excessive wiring, memory and all the
register are connected via a common bus.
• The connection of the registers and memory of the
basic computer to a common bus system is shown in
below fig.
 S2
S1 Bus
S0
Computer Memory unit
4096 x 16
7

Registers
Common AR 1

Bus System PC 2

DR 3

AC 4

INPR

IR 5

TR 6

OUTR
CLOCK
16-bit common bus
• Control variables: Various S2
S1
S0
Bus

control variables are used to Memory unit 7

select: 4096 x 16

• the paths of information and

• the operation of the registers AR 1

• Five registers (AR, PC, DR, AC LD INR CLR

and TR) have three control PC 2

inputs. LD INR CLR

• Load input (LD): DR 3

• Enables the input of a register LD INR CLR
connected to the common bus
• When LD = 1 for a register, the
AC 4
data on the common bus is
read into the register during LD INR CLR
the next clock pulse transition
INPR
• Increment input (INR):
IR 5
• Increments the content of a
register. LD
TR 6
• Clear input (CLR):
LD INR CLR
• Clear the content of a register
to zero OUTR
Clock
LD
16-bit common bus
 S2
S1 Bus
S0
• Memory Address: Memory unit 7
4096 x 16
• The input data and output Address
data of the memory are Write Read

connected to the common AR 1

bus. LD INR CLR

• Memory address is PC 2

connected to AR, So it is LD INR CLR

used to specify a memory DR 3
address. LD INR CLR
• By using a single register for
the address, we eliminate AC 4
the need for an address LD INR CLR
bus.
INPR
• Register  Memory: Write
IR
operation 5
LD
• Memory  Register: TR 6
• Read operation LD INR CLR
• AC can NOT directly read OUTR
Clock
from memory . LD
16-bit common bus
• The Accumulator’s input must S2
S1 Bus
come via the Adder & Logic S0

Circuit. Memory unit

4096 x 16
7

Address
• This allows the Accumulator and
Write Read
Data Register to swap data
simultaneously (same clock cycle) AR 1

• Ex: DRAC, ACDR LD INR CLR

• E is flip-flop (Extended AC) stores PC 2
Carry out of addition. LD INR CLR
• This is done by: DR 3
1- place the contents of AC on the LD INR CLR
bus (S2S1S0=100)
E
2- enabling the LD (load) input of DR Adder
and AC 4
logic
3- Transferring the contents of the LD INR CLR
DR - through the adder and logic
circuit - into AC INPR
4- enabling the LD (load) input of AC IR 5
• Above all steps occur during the LD
same clock cycle TR 6
• The two transfers occur upon the LD INR CLR
arrival of the clock pulse
OUTR
transition at the end of the clock Clock
cycle. LD
16-bit common bus
 S2
S1 Bus
• The outputs of seven S0

registers and memory are Memory unit

4096 x 16
7

connected to the common Address

Write Read
bus.
AR 1
• Selection variables: LD INR CLR
• Used to specify a register PC 2
whose output is connected to LD INR CLR
the common bus at any given
time. DR 3

• To select one register out of 8. LD INR CLR

• (Memory(7=111), AR(1=001), Adder E

PC(2=010), DR(3), AC(4), IR(5), and AC 4
logic
TR(6)), we need 3 select LD INR CLR
variables.
INPR
• The specific output that is
IR 5
selected for the bus is
determined by MUX (S2 S1 S0) LD
TR 6
• For example, if S2 S1 S0 = 011,
LD INR CLR
the output of DR is directed to
the common bus. OUTR
Clock
LD
16-bit common bus
 S2
• When the contents of AR or S1
S0
Bus

PC (12 bits) are applied to Memory unit

4096 x 16
7

the 16-bit common bus, Write Read

Address

• the four most significant bits AR 1

are set to zero.
LD INR CLR
• When AR or PC receives PC 2
information from the bus,
LD INR CLR
only the 12 least significant
bits are transferred to the DR 3

register. LD INR CLR

• Both INPR and OUTR use Adder

and
E
AC 4
only the 8 least significant logic
LD INR CLR
bits of the bus.
INPR
• INPR: Receives a character
from the input device IR 5

(keyboard,…etc) which is then LD

TR 6
transferred to AC
LD INR CLR
• OUTR: Receives a character
OUTR
from AC and delivers it to an Clock
output device (say a Monitor) LD
16-bit common bus
RTL
Register (Capital Letter)
Replacement Operator
Control Function
INSTRUCTION
EXECUTION CYCLE
 Instruction Cycle
• A program is a sequence of instructions stored in
memory.
• An instruction cycle
• is the basic operational process by which a computer
• retrieves a program instruction from its memory,
• determines what actions the instruction dictates, and
• carries out those actions.
• This cycle is repeated continuously by CPU, from boot-up to
when the computer is shut down.
• Each instruction in turn is subdivided into a sequence of
sub-cycles or phases.
• Instruction Cycle Phases:
1- Fetch an instruction from memory
2- Decode the instruction
3- Read the effective address from
memory if the instruction has an
indirect address
4- Execute the instruction
• This cycle repeats indefinitely unless a
HALT instruction is encountered.
Fetch and Decode:
• Initially, the Program Counter (PC) is
loaded with the address of the first
instruction in the program.
• The sequence counter (SC) is cleared to 0,
providing a decoded timing signal T0.
• After each clock pulse, SC is incremented
by one, so that the timing signals go
through a sequence T0, T1, T2, and so on.
• Micro-operations for fetch and decode phases can be
specified by the following statements :

• T0: AR←PC
The address of the instruction is moved to AR.
• T1: IR←M[AR], PC←PC+1
The instruction is fetched from the memory to IR ,
and the PC is incremented.
• T2: D0,…, D7←Decode IR(12-14), AR←IR(0-11), I←IR(15)
 Register Transfer for the Fetch Phase
•T0: AR PC (S2S1S0=010, T0=1)(Load of PC=1)
•T1: IR  M [AR], PC  PC + 1 (S2S1S0=111, T1=1)(Load of IR=1)
•T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
T1 S2

T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus
INSTRUCTIO
N SET
 Table: Basic Computer Instructions
Hexadecimal Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
Memory LDA 2xxx Axxx Load AC from memory
reference STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
Instructions BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
Register CIR 7080 Circulate right AC and E
reference CIL 7040 Circulate left AC and E
INC 7020 Increment AC
Instructions SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

I/O OUT F400 Output character from AC
SKI F200 Skip on input flag
Instructions SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
Register Reference Instructions
•Register Reference Instructions are identified when
• D7 = 1, I = 0
• Register Ref. Instr. is specified in B0 ~ B11 of IR
• Execution starts with timing signal T3.

Fig: Execution of Register Reference Instructions

• r = D7 I’ T3 => Register Reference Instruction
• Bi = IR(i) , i=0,1,2,...,11, the ith bit of IR.

r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer
 MEMORY REFERENCE
INSTRUCTIONS
Symbol Operation Symbolic Description
Decoder
AND D0 AC  AC  M[AR] AND memory word to AC
ADD D1 AC  AC + M[AR], E  Cout Add memory word to AC
LDA D2 AC  M[AR] Load AC from memory
STA D3 M[AR]  AC Store content of AC into memory
BUN D4 PC  AR Branch unconditionally
BSA D5 M[AR]  PC, PC  AR + 1 Branch and save return address
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
Increment and skip if zero
- The effective address of the instruction is in AR and is placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to be completed in a CPU cycle
- The execution of MR Instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
LDA: Load to AC Memory, PC, AR at time T4

D2T4: DR  M[AR] 20 0 BSA 135

Return address: PC = 21 Next instruction
D2T5: AC  DR, SC  0

STA: Store AC AR = 135

D3T4: M[AR]  AC, SC  0 136 Subroutine

BUN: Branch Unconditionally

D4T4: PC  AR, SC  0 1 BUN 135
Memory
BSA: Branch and Save Return Address
Memory, PC after execution
D5T4: M[AR]  PC, AR  AR + 1
20 0 BSA 135
D5T5: PC  AR, SC  0 21 Next instruction

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR] 135 21

D6T5: DR  DR + 1 PC = 136 Subroutine

D6T6: M[AR]  DR, if (DR = 0)

then (PC  PC + 1), SC  0
1 BUN 135
Memory
Input-Output Instructions

• Instructions and data stored in memory must come

from some Input Device.
• Computational results must be transmitted to the
user through some Output Device.
• For the system to communicate with an input device,
serial information is shifted into the input register
INPR.
• To output information, it is stored in the output
register OUTR.
Input-Output Instruction Execution

Serial registers and

Input-output
communication Computer
terminal
interface flip-flops
Receiver
Printer interface OUTR FGO 1-bit Output FlaG

AC

Transmitter
Keyboard interface INPR FGI 1-bit Input FlaG

Serial Communications Path

Parallel Communications Path

Input-Output Instruction Execution

• INPR and OUTR communicate with a

communication interface serially and with
the AC in parallel.
• They hold an 8-bit alphanumeric
information.
• I/O devices are slower than a computer
system  we need to synchronize the
timing rate difference between the
input/output device and the computer.
• FGI: 1-bit input flag (Flip-Flop) aimed to control the
input operation.
• FGI is set to 1 when a new information is available in
the input device and is cleared to 0 when the
information is accepted by the computer.

• FGO: 1-bit output flag used as a control flip-flop to

control the output operation.
• If FGO is set to 1, then this means that the computer
can send out the information from AC. If it is 0, then
the output device is busy and the computer has to
wait…!!
• The process of input information transfer:
• Initially, FGI is cleared to 0
• An 8-bit alphanumeric code is shifted into INPR (Keyboard
key strike) and the input flag FGI is set to 1.
• As long as the flag is set, the information in INPR cannot
be changed by another data entry.
• The computer checks the flag bit;
• if it is 1, the information from INPR is transferred in parallel into
AC and
• FGI is cleared to 0
• Once the flag is cleared, new information can be shifted
into INPR by the input device (striking another key).
• The process of output information:
• Initially, the output flag FGO is set to 1
• The computer checks the flag bit;
• if it is 1, the information from AC is transferred in parallel to
OUTR and
• FGO is cleared to 0
• The output accepts the coded information (prints the
corresponding character)
• When the operation is completed,
• the output device sets FGO back to 1
• The computer does NOT load a new data information into
OUTR when FGO is 0, because this condition indicates that
the output device is busy to receive another information
at the moment….!!
Input-Output Instructions
• Needed for:
• Transferring information to and from AC register.
• Checking the flag bits.
• Controlling the interrupt facility.
• The control unit recognize it when D7=1 and I = 1.
• The remaining bits of the instruction specify the
particular operation.
• Executed with the clock transition associated with
timing signal T3.
• Input-Output instructions are summarized next.
Input-Output Instructions
D7IT3 = p , (common to all I/O instructions)
IR(i) = Bi , i = 6, …, 11 (that specifies the instruction)

p: SC  0
INP F800 pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT F400 pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI F200 pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO F100 pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION F080 pB7: IEN  1 Interrupt enable on
IOF F040 pB6: IEN  0 Interrupt enable off
ADDRESSING MODES
 Addressing Modes
• The way the operands are chosen during program execution is
dependent on the addressing mode of the instruction
• The addressing mode specifies
• a rule for interpreting or
• modifying the address field of the instruction before the operand is
actually referenced
• Purpose of accommodating addressing mode techniques is one
or both of the following:
1. To give programming versatility to the user by providing such facilities
as pointers to memory, counters for loop control, indexing of data, and
program relocation
2. To reduce the number of bits in the addressing field of the instruction
• Adv: writing programs that are more efficient with respect to the
• number of instructions and
• execution time
• An example of an instruction format with a distinct
addressing mode field is shown in below.
• The operation code specifies the operation to be
performed
• The mode field is used to locate the operands needed for
the operation
• There may or may not be an address field in the
instruction
• If there is an address field, it may designate a memory address or
a processor register

Fig: Instruction format with mode field

• Numerical Example

Fig: Numerical example for addressing modes

• Implied Mode:
• the operands are specified implicitly in the definition of
the instruction.
• Example: the instruction "complement accumulator
(CMA)“
• All register use an accumulator are implied-mode instructions
• Example: Zero-address instructions in a stack-organized
computer are implied-mode instructions since the
operands are implied to be on top of the stack
• Immediate Mode:
• the operand is specified in the instruction itself.
• i.e., immediate-mode instruction has an operand field
(contains the actual operand ) rather than an address field
• useful for initializing registers to a constant value

• Register Mode:
• operands are in registers that reside within the CPU
• The particular register is selected from a register field in
the instruction.
• Register Indirect Mode:
• the instruction specifies a register in the CPU whose contents give the
address of the operand in memory
• i.e., the selected register contains the address of the operand rather than
the operand itself
• Advantage : the address field of the instruction uses fewer bits to select a
register to specify a memory address directly

• Auto increment or Auto decrement Mode:

• This is similar to the register indirect mode except that the register is
incremented or decremented after (or before) its value is used to access
memory.
• G
• G
• G
• Direct Address Mode:
• the effective address is equal to the address part of the
instruction.
• The operand resides in memory and its address is given
directly by the address field of the instruction
• In a branch-type instruction the address field specifies the
actual branch address
• Indirect Address Mode:
• the address field of the instruction gives the address
where the effective address is stored in memory
• Control fetches the instruction from memory and uses its
address part to access memory again to read the effective
address
• The effective address (for FEW addressing modes) in these
modes is obtained from the following computation:
effective address = address part of instruction + content of
CPU register
• The CPU register used in the computation may be the
program counter, an index register, or a base register..
• Relative Address Mode:
• the content of the PROGRAM COUNTER is added to the
ADDRESS PART of the instruction in order to obtain the
effective address.
• example,
• assume that the program counter contains the number 825 and
the address part of the instruction contains the number 24.
• The instruction at location 825 is read from memory during the
fetch phase and
• the program counter is then incremented by one to 826.
• The effective address computation for the relative address mode
is 826 + 24 = 850.
• Relative addressing is often used with branch-type
instructions
• Indexed Addressing Mode:
• the content of an INDEX REGISTER is added to the
ADDRESS PART of the instruction to obtain the effective
address
• The index register is a special CPU register that contains an
index value.
• The address field of the instruction defines the beginning
address of a data array in memory.
• The index register can be incremented to facilitate access
to CONSECUTIVE OPERANDS.
• Note : if an index type instruction does not include an
address field in its format, the instruction converts to the
register indirect mode of operation.
• Base Register Addressing Mode:
• the content of a BASE REGISTER is added to the ADDRESS
PART of the instruction to obtain the effective address.
• This is similar to the indexed addressing mode except that
the register is now called a base register instead of an
index register.
• The difference between the two modes is in the way they
are used rather than in the way that they are computed.
• An index register is assumed to hold an index number that is
relative to the address part of the instruction.
• A base register is assumed to hold a base address and the address
field of the instruction gives a displacement relative to this base
address.
• The base register addressing mode is used in computers to
facilitate the relocation of programs in memory.
TABLE: List of Numerical Example
Q:

(Effective address)

A:
A:
Q:

A:
A:
Q:

A:
A:
Q:

A:
A: ZERO
Case study – Instruction set of some common CPUs
CISC & RISC

Complex Instruction Set Computer (CISC)

• The goal is to provide a
• single machine instruction for each statement
• Instruction set consists of
• large number of instructions
• Instructions are of variable-length
• Examples of CISC architectures are the
• Digital Equipment Corporation VAX computer and the IBM
370 computer
IBM 370 –
instruction
formats
ARM
instruction
set formats
X = (A + B) * (C + D)
• The instructions in a typical CISC processor provide
direct manipulation of operands residing in memory.
• For example, an ADD instruction may specify
• one operand in memory through index addressing and
• a second operand in memory through a direct addressing
• Another memory location may be included in the
instruction to store the sum.
• This requires three memory references during execution of
the instruction.
• As more instructions and addressing modes are
incorporated into a computer,
• the more hardware logic is needed to support them
• this may cause the computations to slow down
• Major characteristics of CISC architecture are:
1. A large number of instructions
typically from 100 to 250 instructions
2. Some instructions that perform specialized tasks and are
used infrequently
3. A large variety of addressing modes
Typically from 5 to 20 different modes
4. Variable-length instruction formats
5. Instructions that manipulate operands in memory
Ex:- CISC
RISC Characteristics
• The concept of RISC architecture involves an attempt
to reduce execution time by simplifying the
instruction set of the computer.
• The major characteristics of a RISC processor are:
1. Relatively few instructions
2. Relatively few addressing modes
3. Memory access limited to load and store instructions
4. All operations done within the registers of the CPU
5. Fixed-length and easily decoded instruction format
6. Single-cycle instruction execution
7. Hardwired rather than microprogrammed control
• Other characteristics attributed to RISC architecture
are:
1. A relatively large number of REGISTERS in the processor
unit
1. useful for storing intermediate results
2. registers can transfer information to other registers much faster
2. Use of overlapped register windows to speed-up
procedure call and return
3. Efficient instruction pipeline
4. Compiler support
- for efficient translation of high-level language programs
into machine language programs
Why Overlapped Register Windows
• A procedure call produces a sequence of instructions
that
• save register values,
• pass parameters needed for the procedure, and
• then calls a subroutine to execute the body of the
procedure
• After a procedure return,
• the program restores the old register values,
• passes results to the calling program, and
• returns from the subroutine.
• Saving and restoring registers and passing of
parameters and results involve TIME CONSUMING
operations.
• The overlapped register windows are used to
• provide the passing of parameters and
• avoid the need for saving and restoring register values.
• Each procedure call results in the allocation of a new
window consisting of a set of registers
• Each procedure call
• activates a new register window by incrementing a pointer,
• while the return statement decrements the pointer and
• causes the activation of the previous window.
• Windows have overlapping registers that are shared to
provide the passing of parameters and results.
• The concept of overlapped register windows is
illustrated in below Fig.
Figure:
Overlapped register windows
• The system has a total of 74 registers
• Registers R0 through R9 are global registers
• that hold parameters shared by all procedures
• The other 64 registers are divided into four windows to
accommodate procedures A, B, C, and D
• Each register window consists of
• 10 local registers (used for local variables) and
• two sets of six registers common to adjacent windows (used for
exchange of parameters and results)

(32 registers=
10 global registers + 10 local registers + 6 low overlapping registers +
6 high overlapping registers)
As an example,
• Suppose that procedure A calls procedure B,
• Registers R26 through R31 are common to both procedures
• procedure A stores the parameters for procedure B in these
registers
• Procedure B uses local registers R32 through R41 for local
variable storage.
• If procedure B calls procedure C,
• it will pass the parameters through registers R42 through R47
• When procedure B is ready to return at the end of its
computation,
• the program stores results of the computation in registers R26
through R31 and
• transfers back to the register window of procedure A.
• Registers R10 through R 15 are common to procedures A
and D because the four windows have a circular
organization with A being adjacent to D
• General organization of register windows will have
the following relationships:
• number of global registers = G = 10 (above example )
• number of local registers in each window = L = 10
• number of registers common to two windows = C = 6
• number of windows = W = 4
• The number of registers available for each window is:
• window size = L + 2C + G
• window size is 10 + 12 + 10 = 32 registers (above example )
• The total number of registers needed in the processor
is:
• register file = (L + C)W + G
• register file consists of (10 + 6) x 4 + 10 = 74 registers
(above example )
Q:

A:
A:
Berkeley RISC I
• The Berkeley RISC I is a 32-bit integrated circuit CPU
• It supports
• 32-bit addresses and
• either 8-, 16-, or 32-bit data
• It has a
• 32-bit instruction format (fixed)
• a total of 31 instructions (few)
• There are three basic addressing modes (few) for branch
instructions:
• register addressing
• Immediate operand
• relative to PC addressing
• It has a register file of 138 registers arranged into
• 10 global registers and 8 windows of 32 registers in each (as in
above Fig.)
• the instruction format can specify
• a processor register with a register field of five bits
• Below figure shows the 32-bit instruction formats used
for
• register-to- register instructions
• memory access instructions
Figure: Berkeley RlSC I instruction formats
• For register-to-register instructions,
• the 5-bit Rd field selects one of the 32 registers as a destination
for the result of the operation.
• The operation is performed with the data specified in fields Rs
and S2
• Rs is one of the source registers
• If bit 13 is 0 -- the low-order 5 bits of S2 specify another source register
• If bit 13 is 1 -- S2 specifies a sign-extended 13-bit constant
• Thus the instruction has a three-address format
• second source is a register or an immediate operand
• Memory access instructions (above fig.)
• use Rs to specify a 32-bit address in a register
• S2 to specify an offset
• Register R0 contains all 0's

• The third instruction format

• combines the last three fields to form a 19-bit relative
address Y
• Used with the jump and call instructions
• The COND field replaces the Rd field for jump instructions
• Used to specify one of 16 possible branch conditions
TABLE:
Instruction Set of Berkeley RISC I
(31 instructions)

•31 instructions are grouped

into three categories
• Example, the ADD instruction and how it can be used to
perform a variety of operations:

•Examples of LOAD LONG instructions with different addressing

modes: